Commit Graph

16 Commits

Author SHA1 Message Date
Terje Bergstrom
271456272d gpu: nvgpu: Use FB reg for getting HUB MMU dbg mode
When we program MMU debug mode, we program it to both HUB and GPC
MMU. The query retrieved the value from GPC MMU, which introduces
a dependency from FB to GR. Change the code to retrieve the mode
from HUB MMU instead.

Change-Id: I6fa98e050480f7405395b7e44965defa386734d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801419
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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2018-08-27 21:44:34 -07:00
Terje Bergstrom
dd71ad91b9 gpu: nvgpu: Implement own ACR code for scrubber
Implement HW scrubber specific code for filling in ACR header. The
PMU code relied on PMU debug mode for choosing between dbg/prod
signature, and also introduced a direct dependency from FB to ACR.

Change-Id: I08fa31538bec3dcb5d161a6e7076ffad76129a97
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801418
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2018-08-27 21:44:30 -07:00
Terje Bergstrom
6662188868 gpu: nvgpu: Do not refer to RAM_IN fields in FB
Do not refer to bit width in RAM_IN field when shifting MMU fault
buffer entries. Export the correct bit shift values for the fields
and shift with that.

Change-Id: I6878118bb14f070626e8244d5044b6818c8ea283
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801417
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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2018-08-27 21:44:21 -07:00
Terje Bergstrom
6f57a339ee gpu: nvgpu: gv100: Remove extra UART spew
Remove extra UART spew in fb_gv100.c. We were using nvgpu_info()
instead of nvgpu_log_info().

Change-Id: Ideb44e492a76ca2f58c14b445bb0a31ebe4c995a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805692
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2018-08-27 10:23:42 -07:00
Konsta Holtta
3bd47da095 gpu: nvgpu: add missing timer includes
Many files used declarations from timers.h implicitly via another header
file(s). Add several #includes explicitly to their users.

Jira NVGPU-967

Change-Id: I88b515061db87c69bd85e3655b74d0271a80d9bf
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804611
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2018-08-24 14:57:57 -07:00
Terje Bergstrom
f062cc5b24 gpu: nvpgu: Remove dependency from FB to Falcon
FB had a dependency to Falcon headers because it was doing debug
dump of registers. Remove the debug dump to get rid of the dependency.

JIRA NVGPU-1063

Change-Id: I15c259b66ce58fd327e974c8d66b6be764e61fed
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801416
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2018-08-24 14:57:14 -07:00
Terje Bergstrom
a9bb03799e gpu: nvgpu: FB does not depend on TOP
fb_gm20b.c does not use anything from hw_top_gm20b.h. Remove the
include directive.

JIRA NVGPU-1063

Change-Id: Ia010fe00a55cc10c3394f9cbfd3ead4ae3c05b4e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801415
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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2018-08-24 14:57:10 -07:00
Terje Bergstrom
09aa5f1fb4 gpu: nvgpu: Do not reset FB
The fields for resetting FB have been defunct since Maxwell, and
FB and related units are powered up by default. Remove accessing
the resets.

JIRA NVGPU-1063

Change-Id: I3de23134e56408cc32321717d55d23a4d7af3140
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801414
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2018-08-24 14:57:07 -07:00
Srirangan
9e69e0cf97 gpu: nvgpu: common: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I599cce2af1d6cdc24efefba4ec42abfe998aec47
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795845
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2018-08-20 05:46:25 -07:00
Vinod G
c9f8f1ea05 gpu: nvgpu: remove utils.h from gk20a.h
Removed the utils.h include from gk20a.h
utils.h is included in those files which
make use of the macros in utils.h

JIRA NVGPU-1005

Change-Id: Ifb41da58db6ff8682fa6b5dfdd8eda11a751fcac
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1785952
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2018-08-10 18:11:26 -07:00
Aparna Das
9c13b30a46 gpu: nvgpu: make cbc alloc os specific
CBC base needs to be aligned to 64KB. On Linux this is
achieved making compbit backing size multiple of 64KB.
However QNX nvmap alloc function does not allocate
memory aligned to requested size and needs to overallocate
to satisfy alignment requirement. Make cbc alloc function OS
specific to be able to modify QNX code.

Also align cbc base address to 64KB before writing to CBC BASE
register.

Bug 200426427

Change-Id: Ic867501403f2e2a4ba41ad5a8ed6f9c5c8ffa3f4
Signed-off-by: Aparna Das <aparnad@nvidia.com>
(cherry picked from commit 3f1e1133a46ebfc9763c649d7b839d069cae5a36)
Reviewed-on: https://git-master.nvidia.com/r/1786046
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2018-08-09 18:45:42 -07:00
Debarshi Dutta
82a90170d3 gk20a: nvgpu: Remove io.h dependency from gk20a.h
In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h

JIRA NVGPU-597

Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
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2018-07-30 11:24:06 -07:00
Vinod G
509139b8a0 gpu: nvgpu: Rearrange the static inline code
In order to avoid the circular dependencies,
rearrange the static inline functions from
gk20a.h file.

Moved gk20a_gr_flush_channel_tlb function to
gr_gk20a.c and removed the #include gr_gk20a.h
from gk20a.h

Added a helper function utils.h to
move all generic static inline functions which
have no reference to gpu related structures.

ptimer related functions are moved to
ptimer.h

Implementations for as and pmu are moved to
corresponding files.

JIRA NVGPU-624

Change-Id: I4e956326e773ba037bf3a1696cc4c462085dbbe5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1781941
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2018-07-24 16:11:07 -07:00
Richard Zhao
7f14aafc2c gpu: nvgpu: rework ecc structure and sysfs
- create common file common/ecc.c which include common functions for add
  ecc counters and remove counters.
- common code will create a list of all counter which make it easier to
  iterate all counters.
- Add chip specific file for adding ecc counters.
- add linux specific file os/linux/ecc_sysfs.c to export counters to
  sysfs.
- remove obsolete code
- MISRA violation for using snprintf is not solved, tracking with
  jira NVGPU-859

Jira NVGPUT-115

Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1763536
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2018-07-19 16:43:58 -07:00
Seema Khowala
b1d0d8ece8 Revert "Revert: GV11B runlist preemption patches"
This reverts commit 0b02c8589d.

Originally change was reverted as it was making ap_compute test on
embedded-qnx-hv e3550-t194 fail. With fixes related to replacing tsg
preempt with runlist preempt during teardown, preempt timeout set to
100 ms (earlier this was set to 1000ms for t194 and 3000ms for legacy
chips) and not issuing preempt timeout recovery if preempt fails, helped
resolve the issue.

Bug 200426402

Change-Id: If9a68d028a155075444cc1bdf411057e3388d48e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762563
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2018-07-19 13:54:26 -07:00
Terje Bergstrom
b97bcb3c68 gpu: nvgpu: Move FB to common
Move all FB HAL implementations to common/fb.

JIRA NVGPU-596

Change-Id: Id4ea09d608f5d6d1b245bddac09ecf1444b8ab30
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769724
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2018-07-12 20:44:13 -07:00