JIRA DNVGPU-129
1)send 150'c as default temperature to PMU so that PMU will
start reading temperature from sensor to evaluate VFE equations
2)Send GP106's temp min and max range for GPU sensor so that PMU
will read right temperature
3)PMU will send event whenever temperature goes above +ve hysteresis
or goes below -ve hysteresis. Call the Arbiter's VF re-evaluation
function in the event handler.
Change-Id: Iaebc0655f60e17998f0864824095f4fc8bba5b62
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1245392
(cherry picked from commit 7e59d0faa8cee6aace5524c724001e88248b2da7)
Reviewed-on: http://git-master/r/1268062
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
The current code can lead to application hang when
opening device on first time if the arbiter fails
to set the clocks
Also it solves a buffer overrun condition in case
the requested frequency is above the maximum range
of the VF curve
bug 1835042
Change-Id: I385401ea27d5cc4bfa41b7ca2eb3a1db53138418
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1245911
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1268061
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Modification of the arbiter to remove all locking
from the arbiter callback and move the callbacks
out of the global queue
Adding modification to call for updated values of
vf table from arbiter init function and on
vf table update
JIRA: DNVGPU-170
Change-Id: I7a7d34c0590522901e06356c06fd8114ebf10f37
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1243212
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1268009
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
(1) modified counters debug code to export to the driver
(2) modified arbiter to read from those functions
(3) modified counter for higher accuracy on MHz range
JIRA DNVGPU-164
Change-Id: I2bbf7c9be4dc59718d1d91c53028a39020b5aea5
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239467
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1268008
JIRA DNVGPU-143
The arbiter is charged with selecting the proper
frequencies when multiple applications submit
simultaneously clock change requests
On the current implementation, the arbiter guarantees
that the selected frequency will be always higher
or equal to the request, as long as the request is
in range.
The current code is not yet realtime friendly, as
requests are not pre-allocated.
Summary of changes:
(1) pstate/vf switch no longer selects boot frequency
(2) changed mclk code change to accept input freq
(3) added arbiter
(4) now a single session can submit concurrent requests
the last request is the one that applies for that
session
(5) modified locking mechanism to reduce lock contention
(6) Added callback to notify the arbiter that the VF
table has changed and is no longer valid (PMU/Thermals
must call this when VF table is invalid)
(7) changed internal API to work with MHz
(8) added debugfs for stats
Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239461
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1267120
Reviewed-by: Automatic_Commit_Validation_User
Use the bootstrap base address for calculating the address of WPR.
The bootstrap base is dynamic and depends on amount of memory, so
we should not hard code any address.
Bug 200244445
Change-Id: Ia700d24c8d572a25946f7b1847faec72c40c6796
Signed-off-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1242252
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-on: http://git-master/r/1267125
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Remove FB ISO clock gating register from initializion list. The
register does not exist on GPUs without own memory.
Change-Id: I86a8c8050baad88a99029771511363f2a1d44341
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1265297
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Install one completion fd per SET request.
Notifications on dedicated event fd.
Changed frequencies unit to Hz from MHz.
Remove sequence numbers from dummy arbiter.
Added effective clock type (query frequency from counters).
Jira DNVGPU-125
Change-Id: Id5445c6ae1d6bf06f7f59c82ff6c5d3b34e26483
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1230239
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit d17083f4ceb69725c661678607a3e43148d38560)
Reviewed-on: http://git-master/r/1243106
Add clock arbiter skeleton with support of clock sessions,
notifications on clock changes, request numbering, and asynchronous
handling of clock requests. Provides minimum behaviour to allow
unit tests implementation. Actual arbitration and clock settings
will be done separately. For now, dummy arbiter keeps last
requested target mhz. Actual arbiter may move to a lockless
implementation.
Jira DNVGPU-125
Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1223476
(cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461)
Reviewed-on: http://git-master/r/1243105
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
We can trigger CILP only if SM debug mode is on.
So in fecs interrupt handler, we could have graphics context
running for which SM debug mode is disabled.
And in that case we skip posting of cilp completion
events to UMD.
But since CILP event was anyways triggered, we need to post
events to UMD irrespective of SM debug mode is enabled
at that point or not
Hence remove check gk20a_gr_sm_debugger_attached() for
posting events to UMD
Bug 200243092
Change-Id: I54ad205be11ec6d5034d524bfbb28f8a1fa72993
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1263591
(cherry picked from commit e6259e2d0d5a4bb5929e70e03e154f8b82ae3600)
Reviewed-on: http://git-master/r/1264780
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
gp10b does not have an fbpa unit, although the
hw header files claim it does. Hardcode all fbpa
values to 0.
Bug 200249125
Change-Id: I6ed63b3231d7af8e31ccf5047d56bdb85f05a9d9
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1256422
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
In gp10b_ce_nonstall_isr(), we trigger a semaphore wakeup.
Currently, we clear the interrupt status register after the
wakeup is complete. There is potential for an interrupt to
come in while the wake-up operation is in progress, and it
is possible that:
1) We miss processing the interrupt in that ISR iteration AND
2) We clear the interrupt status register anyways
This change clears the status register before triggering wakeup,
so the interrupt will properly re-fire.
Bug 200244458
Change-Id: Ia3338252eeea4eb60d11c0e241279989a46dac04
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1253107
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Expose the currently hard coded boot frequency, which is at the same
time the max frequency. We use it for filling in GPU characteristics.
Bug 200251486
Change-Id: I3c0abb7a385a83f61b93ddfa857b982c850853e3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252906
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
get_litter_value API is updated to use int instead of
enum type.
JIRA GV11B-21
Change-Id: I982fdfe372f4be38aa4ed026a23e936d73190e79
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1252212
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Fix small problems related to signed versus unsigned comparisons
throughout the driver. Bump up the warning level to prevent
such problems from occuring in future.
Change-Id: Ib7026728ef0e8c3c9e68956fc9794ec3a786a8a2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252069
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GPU frequencies can be set by powerhal when GPU is railgated,
and before this change that would cause EMC floors to remain
set until GPU is unrailgated.
After this change, EMC floors are not requested by the GPU
client when the GPU is railgated. It is ok to ignore the
requests, as the GPU client maxes the floor when powering
up.
Bug 1807560
Change-Id: I9a0d58b0288edbd03b2edf09580ecabd9b74f0c2
Signed-off-by: Juha Lainema <jlainema@nvidia.com>
Reviewed-on: http://git-master/r/1216233
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Cyril Raju <craju@nvidia.com>
Tested-by: Cyril Raju <craju@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add regops whitelists for gp106. The whitelist is generated, and is the
same for context switched and global registers.
Bug 200239422
Change-Id: Ib6689956c191c8f346da8cc5c7e3791f105db4eb
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1243253
(cherry picked from commit 1bdc23c9f9aac7ba91a50b83397925237851f8db)
Reviewed-on: http://git-master/r/1247645
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Due to missing break statements, GPC base and GPC shared base were
overwritten by values in following select cases.
Change-Id: Iba50d8256c1cf07ff8e631e2fcf22a68cdc992e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249970
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
- Define fuse macros depending on kernel version as fuse
offset got changed in K4.4 and for K4.4 fuse defines are
defined in common header file (tegra-fuse.h)
- Use fuse control read/write APIs when reading control
registers for K4.4
Bug 200243956
Change-Id: I34dabd1a307d10010cb89ac6a5f1e3f5b177c0fc
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1245825
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
- Read voltage tables from VBIOS & construct
then send to PMU.
- compare & set voltage based on
mclk/gpc2clk clk, take higher voltage
between two & set.
JIRA DNVGPU-122
Change-Id: I23e7b101a3b1c1b6596620fc6b8319c70bd9a488
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1224365
(cherry picked from commit e0055c3ec798b8312df3fa9bf92bde8c57c6f58c)
Reviewed-on: http://git-master/r/1244657
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
- changes to read voltage tables from VBIOS
& create boardobj then send to pmu
- Rail, Device & Policy objects are read from VBIOS & created boardobjs
- RPC support to load, Set & get voltage.
JIRA DNVGPU-122
Change-Id: I61621a514eef9c081a64c4ab066f01dfc28f8402
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1222774
(cherry picked from commit 9da86d8c2c547623cf5f38c89afeb3f5bb1667ac)
Reviewed-on: http://git-master/r/1244656
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This CL covers the following implementation,
1) Power Sensor Table parsing.
2) Power Topology Table parsing.
3) Add debugfs interface to get the current power(mW), current(mA) and
voltage(uV) information from PMU.
4) Power Policy Table Parsing
5) Implement PMU boardobj interface for pmgr module.
6) Over current protection.
JIRA DNVGPU-47
Change-Id: I7b1eefacc4f0a9824ab94ec8dcebefe81b7660d3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1217189
(cherry picked from commit ecd0b16316cb4110118c6677f5f03e02921c29b6)
Reviewed-on: http://git-master/r/1241953
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
JIRA DNVGPU-123
now a function can be called with GPC2CLK value
It will take care calculating slave clock values
and calling VF inject to program clock
Made programming of boot clock code to use this
newly created function.
Change-Id: I74de7e9d98e379e94175ed2d9745ce3ab6c70691
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1221976
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1235056
JIRA DNVGPU-123
Function will copy possible clock points for
a given master clock domain to pointer passed.
pointer with NULL value and count of zero can be passed
to query number of clock points for a given domain so that
memory can be allocated and function called again to
fill clock points
Change-Id: Iec6206f23789980036be99793599e934bd221035
Reviewed-on: http://git-master/r/1218912
(cherry picked from commit 9219697bff1e12deb605325055a02a7b387996e9)
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1235055
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
JIRA DNVGPU-123
function was added to retrieve V for F or
F for V for a given clock domain.
Clock domain can be master or slave.
F or V can be intermediate point between two
successive V or F values in VF table.
VF table should be cached before calling this function.
A F value below Fmin will return Vmin.
F > Fmax will return error
A V value above Vmax wil return F max.
A V value below Vmin will return error.
Change-Id: I28b4e8647510c6933e9e1204cfff31d74616e11a
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1211234
(cherry-picked from commit 5b83b03f2454fbec8d49a064ed09b09c92d3e9fa)
Reviewed-on: http://git-master/r/1235054
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
We need to wait for scrubber to have finished before we can allow
any accesses to memory. Do the wait in place where on iGPU we would
do FB reset.
Bug 1799537
Bug 1815139
Change-Id: Ic92dee936388a13c4abf0b295fd99581522c430f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1235541
(cherry picked from commit 1ef73ecb4e37da042e7117426ab2823b7f4528dc)
Reviewed-on: http://git-master/r/1239955
GVS: Gerrit_Virtual_Submit
bug 200088648
sparse warning reported that the function was not
defined. This was due to a missing include
Change-Id: Ia6153a2f3348a86e78add95bcfff998505b47cdd
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1237845
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
