Add macros to get current GR instance id and the pointer
nvgpu_gr_get_cur_instance_ptr()
nvgpu_gr_get_cur_instance_id()
This approach makes sure that the caller is getting GR instance pointer
under mutex g->mig.gr_syspipe_lock in MIG mode. Trying to access
current GR instance outside of this lock in MIG mode dumps a warning.
Return 0th instance in case MIG mode is disabled.
Use these macros in nvgpu instead of direct reference to
g->mig.cur_gr_instance.
Store instance id in struct nvgpu_gr. This is to retrieve GR instance
id in functions where struct nvgpu_gr pointer is already available.
Jira NVGPU-5648
Change-Id: Ibfef6a22371bfdccfdc2a7d636b0a3e8d0eff6d9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413140
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Add a new header file <nvgpu/gr/gr_instances.h> that supports below
macros to execute various functions for GR instances
1) nvgpu_gr_exec_for_each_instance
Execute a function for each GR instance by configuring GR remap
window for that instance. Function being executed returns void.
2) nvgpu_gr_exec_with_ret_for_each_instance
Execute a function for each GR instance by configuring GR remap
window for that instance. Function being executed returns an error.
3) nvgpu_gr_exec_for_all_instances
Execute a function for all GR instances at once. For this GR remap
window needs to be disabled temporarily.
If CONFIG_NVGPU_MIG is disabled, all above macros will turn into simple
funciton calls.
If CONFIG_NVGPU_MIG is disabled or if runtime flag NVGPU_SUPPORT_MIG is
disabled, all above macros will turn into simple function calls that
configure single GR instance.
Separate out GR engine reset code into new API gr_reset_engine() and
execute it with nvgpu_gr_exec_with_ret_for_each_instance().
PROD values need to be loaded in legacy mode, hence call
nvgpu_cg_init_gr_load_gating_prod() inside
nvgpu_gr_exec_for_all_instances().
Rename gr_init_prepare_hw() to more appropriate
gr_reset_hw_and_load_prod()
Moe gops.gr.init.fifo_access() call to gr_init_reset_enable_hw().
Add new API nvgpu_grmgr_get_gr_syspipe_id() to query GR instance syspipe
id from common.grmgr unit. Add nvgpu_gr_get_syspipe_id() that returns
same value stored in nvgpu_gr struct.
Add cur_gr_instance field to struct nvgpu_gr to track current GR
instance being programmed under remap window.
Jira NVGPU-5648
Change-Id: I86920303427a6e6547ebf195daa37438365bb38e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2403550
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Add doxygen documentation for private GR structures defined in:
gr/gr_config_priv.h
gr/gr_falcon_priv.h
gr/gr_intr_priv.h
gr/gr_priv.h
Remove "p_va" field from struct nvgpu_ctxsw_ucode_info since it is
unused.
Compile out "pm_ctxsw_image_size" with flag CONFIG_NVGPU_DEBUGGER.
Compile out "preempt_image_size" with flag CONFIG_NVGPU_GRAPHICS.
Replace eUcodeHandshakeInitComplete enum value by macro
FALCON_UCODE_HANDSHAKE_INIT_COMPLETE. And remove enum value
eUcodeHandshakeMethodFinished since it is unused.
Compile "ctxsw_disable_mutex" and "ctxsw_disable_count" in struct
nvgpu_gr only if CONFIG_NVGPU_RECOVERY or CONFIG_NVGPU_DEBUGGER is
defined
Jira NVGPU-4028
Change-Id: Ie8769c1f3f8d313b479b182d3858a6715d49cd4c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201373
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Overriding of ECC feature is used only in Linux through device
tree fuse overrides. It's not supported in QNX. Hence compile
out below functions from safety build.
nvgpu_gr_get_override_ecc_val()
nvgpu_gr_override_ecc_val()
Move nvgpu_gr_get_golden_image_ptr() under CONFIG_NVGPU_DEBUGGER
Re-arrange all functions in gr_utils.c/h and move all non-safe
functions towards end of file.
Jira NVGPU-4028
Change-Id: Ie56fcf78c32a9b23d2e5f5b51701c5f8ccad62ec
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199507
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
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create a new unit common.fbp which initializes fbp support and provides
APIs to retrieve fbp data.
Create private header with below data
struct nvgpu_fbp {
u32 num_fbps;
u32 max_fbps_count;
u32 fbp_en_mask;
u32 *fbp_rop_l2_en_mask;
};
Expose below public APIs to initialize/remove fbp support:
nvgpu_fbp_init_support()
nvgpu_fbp_remove_support()
vgpu_fbp_init_support() for vGPU
Expose below APIs to retrieve fbp data
nvgpu_fbp_get_num_fbps()
nvgpu_fbp_get_max_fbps_count()
nvgpu_fbp_get_fbp_en_mask()
nvgpu_fbp_get_rop_l2_en_mask()
Use above APIs to retrieve fbp data in all the code.
Remove corresponding fields from struct nvgpu_gr since they are no
longer referred from that structure
Jira NVGPU-3124
Change-Id: I027caf4874b1f6154219f01902020dec4d7b0cb1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108617
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.
Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);
JIRA NVGPU-3214
Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
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max_ctxsw_ring_buffer_size variable in struct nvgpu_gr is used to store
max ring buffer size which is then referred into linux specific code
We only use macro GK20A_CTXSW_TRACE_MAX_VM_RING_SIZE to initialize
the variable.
And max_ctxsw_ring_buffer_size does not belong to nvgpu_gr struct
anyways
Considering above remove max_ctxsw_ring_buffer_size from nvgpu_gr and
use macro directly in linux specific code
Jira NVGPU-3125
Change-Id: Ibed9901d2bde35633d9ad0df8bd08b414e075bf4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105653
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Currently max_css_buffer_size is incorrectly stored in struct nvgpu_gr
Add a new hal g->ops.css.get_max_buffer_size() to get the size and
remove the variable from struct nvgpu_gr
Jira NVGPU-3125
Change-Id: If78fd86559526b84031051e281a98327a46fc11d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105652
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cyclestats_snapshot data and lock is right now stored in struct nvgpu_gr
Use case itself is not specific to GR engine but in general it applies
to other units outside of GR too.
Hence it makes sense to move both data and lock to struct gk20a instead
of keeping them in struct nvgpu_gr
Update all cyclestats_snapshot code to refer data/lock from struct gk20a
Remove gr_priv.h header include from cyclestats_snapshot.c
Some of the functions were mistakenly declared in gr_gk20a.h.
Move them to cyclestats_snapshot.h and rename them to form nvgpu_css_*()
Jira NVGPU-1103
Change-Id: I3fb32fe96f0ca6613f4640c8bd227b9e0e02dca3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104848
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gr_gk20a.ctx_vars struct right now stores sizes for golden_image, zcull,
pm_ctxsw, and gfxp_preemption_buffer.
but these sizes should be really owned by respective units and should
be assigned to units as soon as they are queried from FECS
Add new structure to nvgpu_gr_falcon to hold sizes that will be queried
from FECS
struct nvgpu_gr_falcon_query_sizes {
u32 golden_image_size;
u32 pm_ctxsw_image_size;
u32 preempt_image_size;
u32 zcull_image_size;
};
gr.falcon unit now queries sizes from FECS and fills this structure.
gr.falcon unit also exposes below APIs to query above sizes
u32 nvgpu_gr_falcon_get_golden_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_pm_ctxsw_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_preempt_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_zcull_image_size(struct nvgpu_gr_falcon *falcon);
gr.gr unit now calls into gr.falcon unit to initailize sizes, and then
uses above exposed APIs to set sizes into respective units
vGPU will too fill up struct nvgpu_gr_falcon_query_sizes with all the sizes
and then above APIs will be used to set sizes into respective units
All of above means size variables in gr_gk20a.ctx_vars struct are no more
being referred. Delete them.
Jira NVGPU-3112
Change-Id: I8b8e64ee0840c3bdefabc8ee739e53a30791f2b3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103478
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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struct gr_gk20a defines boolean flag golden_image_initialized to
indicate if golden_image is initialized or not
common.gr.obj_ctx also added a flag of its own to check if golden_image
is ready
Add new API nvgpu_gr_obj_ctx_is_golden_image_ready() in
common.gr.obj_ctx unit to get status of golden_image
Use this new API everywhere to check if golden image is ready
Remove g->gr.ctx_vars.golden_image_initialized
Also remove ctx_mutex from struct gr_gk20a
Add new flag golden_image_initialized to struct nvgpu_pmu_pg and set it
when golden image is initialized. This is needed to avoid circular
dependency between GR and PMU
Jira NVGPU-3112
Change-Id: Id391294cede6424e15a9a9de29c40d013b509534
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099400
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Basic units like fifo, rc are having dependency on
gr_falcon. Avoided outside gr units dependency on gr_falcon
by moving following functions to gr:
int nvgpu_gr_falcon_disable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_disable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_enable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_enable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_halt_pipe(struct gk20a *g); ->
int nvgpu_gr_halt_pipe(struct gk20a *g);
HALs also moved accordingly and updated code to reflect this.
Also moved following data back to gr from gr_falcon:
struct nvgpu_mutex ctxsw_disable_mutex;
int ctxsw_disable_count;
JIRA NVGPU-3168
Change-Id: I2bdd4a646b6f87df4c835638fc83c061acf4051e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100009
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
