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vinodg
363ecdf9be gpu: nvgpu: add fault injection for nvgpu_readl 
Add fault injection handling for nvgpu_readl() API.
Function return zero on fault injection.

Jira NVGPU-4453

Change-Id: If1b131811bde38e9a22f02e48f53726a03f51d08
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265045
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 2020-12-15 14:10:29 -06:00
Rajesh Devaraj
61014ee0f9 gpu: nvgpu: update nvgpu_posix_fault_inj_container 
This patch updates nvgpu_posix_fault_inj_container for qnx.os.intr.
Specifically, it adds the following members:
 - qnx_intattach_event_fi
 - qnx_int_wait_fi

JIRA NVGPU-2694

Change-Id: I8dfaa496ddf96dbf6e61f567f2d23378b61dc4f8
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263055
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Reviewed-by: Prateek Sethi <prsethi@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Adeel Raza
28514b49fb gpu: nvgpu: convert disable_syncpoints into a bool 
The disable_syncpoints debugfs knob allows the user to disable syncpt
support at runtime. This knob was incorrectly defined as a u32. Convert
it into a boolean variable.

JIRA NVGPU-3873

Change-Id: If1cfe07fa7b795c0d1b507395bd6e4fa547e3615
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262193
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 2020-12-15 14:10:29 -06:00
Adeel Raza
f121724cce gpu: nvgpu: MISRA comment fixes 
MISRA doesn't allow embedding // comments inside a /* */ comment. Fix
a couple of these violations in static_analysis.h.

JIRA NVGPU-3873

Change-Id: Ied2b62bad7379d83ded7a4c24b49627c6e79e614
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262192
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 2020-12-15 14:10:29 -06:00
Adeel Raza
6b771b06be gpu: nvgpu: safety build related MISRA fixes 
Clean up a couple of MISRA violations for functions which are not being
compiled in the safety build.

JIRA NVGPU-3873

Change-Id: Iaaf03c9590bc85d5d411b10363c23266df5630c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262191
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 2020-12-15 14:10:29 -06:00
Adeel Raza
fd870b300e gpu: nvgpu: rename nvhost_dev to nvhost 
A couple of structure member variables were named "nvhost_dev". This
causes a name conflict with a structure name. MISRA frowns upon name
conflicts. Therefore, rename the member variables to "nvhost".

JIRA NVGPU-3873

Change-Id: I4d35eb2d121b3c17499055d8781a61641594811e
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262190
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 2020-12-15 14:10:29 -06:00
Adeel Raza
26af1c2270 gpu: nvgpu: MISRA integer fixes 
Apply various MISRA integer related fixes. Some fixes simply required
adding a "U" suffix to integer constants. Other fixes were more
complicated and required breaking up complex composite expressions into
multiple smaller expressions.

JIRA NVGPU-3873

Change-Id: Id8a08a17d1cf9e20193bd3e4f2d4104774d81767
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262189
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 2020-12-15 14:10:29 -06:00
Adeel Raza
eb0b0c78d4 gpu: nvgpu: sync: remove snprintf usage 
snprintf() usage is banned by MISRA because it uses variable arguments.
Replace snprintf() with other string operations.

JIRA NVGPU-3873

Change-Id: I22205f91500c997c155fe1759ccea90b3f481d59
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262188
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 2020-12-15 14:10:29 -06:00
Adeel Raza
7c634f2489 gpu: nvgpu: error related MISRA fixes 
Fix various MISRA violations related to error codes returned by
functions. These error codes were not being handled/checked.

JIRA NVGPU-3873

Change-Id: Id9a6caefe43248c4e22423cda3bac0ceeb9f47c9
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262187
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 2020-12-15 14:10:29 -06:00
Adeel Raza
a4b8ec00b3 gpu: nvgpu: MISRA fixes for limit macros 
Limit macros from the C library's limits.h are not always in the desired
variable type. Cast these macros to the appropriate variable type to fix
MISRA violations.

JIRA NVGPU-3873

Change-Id: Ib06327aaa6cb78e4a5026b8fc4c15ce356140cc4
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262186
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
f3421645b2 gpu: nvgpu: compile out fb and ramin non-fusa code 
fbpa related functions are not supported on igpu safety. Don't
compile them if CONFIG_NVGPU_DGPU is not set.
Also compile out fb and ramin hals that are dgpu specific.
Update the tests for the same.

JIRA NVGPU-4529

Change-Id: I1cd976c3bd17707c0d174a62cf753590512c3a37
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265402
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
1ec4a4f8ec gpu: nvgpu: fix Cert-C errors in vm.c 
INT30-C requires that unsigned integer operations do not wrap. This
patch adds safe operation APIs to resolve Cert-C errors.

Jira NVGPU-4677

Change-Id: I7dad28e8de9fe8ea1bdc0ca33b8cebe103cac5a7
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264218
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
a50802510f gpu: nvgpu: unit: improve coverage for gv11b pbdma HAL 
Improve branch coverage for the following HALs:
- gv11b_pbdma_handle_intr_0 (add error cases for report_pbdma_error)
- gv11b_pbdma_handle_intr_1 (add HCE interrupt case)

Jira NVGPU-3694
Jira NVGPU-4673

Change-Id: I658a7c270af16152ccb6a0b19da1fa8c68e9c2ec
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263669
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
31d689d489 gpu: nvgpu: unit: improve coverage for gm20b pbdma HAL 
Add unit test for the following HAL:
- gm20b_pbdma_get_ctrl_hce_priv_mode_yes

Jira NVGPU-3694
Jira NVGPU-4673

Change-Id: Ie6c0266753877b5fe7a5c32bf6b971d1ef34d724
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263651
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
5629bd900c gpu: nvgpu: remove dead code in gm20b_pbdma_acquire_val 
Removed BUG_ON statements from gm20b_pbdma_acquire_val, as
condition could never be true. The only overflow that can
happen is in nvgpu_safe_mult_u64.

Compute exponent by shifting timeout (in units of 1024 ns)
until it fits into mantissa. This removes the need to
compute most significant bits, and allows using hw definitions
for mantissa and exponent max values.

Jira NVGPU-3694
Jira NVGPU-4673

Change-Id: Iaf4b5aaafe5b4e759d4e447f76f05f81e201a584
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263650
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 2020-12-15 14:10:29 -06:00
Seeta Rama Raju
2e03e88431 gpu: nvgpu: Add fault injection for clk unit 
- Adding fault injection for clk api's in embedded_lib mocks.

JIRA NVGPU-2682

Change-Id: If10c78fc4cb57c6788aebafa55d270a8119f7ca7
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260178
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 2020-12-15 14:10:29 -06:00
vinodg
8ab5e07d8f gpu: nvgpu: Update for gr config code coverage. 
Replace if statement with nvgpu_assert,this checking is just to
assure following division will not cause system crash.

Jira NVGPU-4531

Change-Id: I213882b56ccfd993066c58bc3fb6c47a6fd92d4a
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264410
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
569b781cb2 gpu: nvgpu: unit: skip falcon dump for fifo intr 
Register address space for falcon is not registered
and g->ops.gr.falcon.dump_stats is triggering multiple
ABORTs while testing gv11b_fifo_intr_0_isr.

Use stub for g->ops.gr.falcon.dump_stats.

Jira NVGPU-4386

Change-Id: I6fb2b9b59f533626fce49bf4d3ff72cb8a1a6c44
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Prateek sethi
28d21878a7 gpu: nvgpu: fix memory fault in invalid_pd_alloc 
nvgpu_pd_alloc() calls gk20a_from_vm which is extracting g from
vm->mm->g without assigning mm pointer to vm->mm. Assigning the
pointers.

Bug 200577095

Change-Id: Ibe2757b0616fd8e87df509abe5d85e90d989d45c
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264751
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 2020-12-15 14:10:29 -06:00
Philip Elcan
ae8f71a462 gpu: nvgpu: unit: add therm unit test 
Add unit test for common.therm and gv11b therm HALs.

JIRA NVGPU-936

Change-Id: Iff857ad24eac729b5f7bf9868c1f05becefbaaad
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
3610dec176 gpu: nvgpu: posix: allow unit tests to simulate simulation 
Add a flag in the unit test posix shim to be able to report driver is
running in simulation when calling nvgpu_platform_is_simulation.

JIRA NVGPU-936

Change-Id: I8647e6721135e85cfadaa2248d081c76ca942c74
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260440
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
fadcf3ab7f gpu: nvgpu: therm: move non-fusa therm hal 
The HAL gm20b_therm_init_blcg_mode() is not used in FUSA builds, so move
it to the non-FUSA file.

This leaves the file therm_gm20b_fusa.c without code, so remove that
file.

JIRA NVGPU-936

Change-Id: Id3cb4e65035654ef5823906794544005e4e48de2
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260439
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 2020-12-15 14:10:29 -06:00
vinodg
3400d1b6be gpu: nvgpu: branch coverage for gr.falcon hal 
Update gr.falcon hal test for branch coverage.
Generate expected bug by passing 64bit value for falcon.bind_instblk.

Jira NVGPU-4453

Change-Id: I735f96f21e54fce199a47c37043acc81006ee806
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264321
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
2f9548c1f8 gpu: nvgpu: Add test cases for ACR construct execute code 
Adding more test cases to cover fail/negative scenarios
and more branches in the nvgpu_acr_construct_execute() code

JIRA NVGPU-4319

Change-Id: I998f914abf9ba592a3a014698efaa2437236f448
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263868
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
61315f0fbb gpu: nvgpu: Add test cases for HS bootstrap code 
Adding more test cases to cover fail/negative scenarios
and more branches in the nvgpu_acr_bootstrap_hs_acr() code

JIRA NVGPU-4319

Change-Id: Ib8b154f7e59e60971bb231cf7dbe0b9b3f209384
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
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 2020-12-15 14:10:29 -06:00
ddutta
83103cdcca gpu: nvgpu: move set_min_max out of safety build 
nvgpu_channel_sync_set_min_eq_max is not used as part of the safety
build and hence is moved out. channel_sync_syncpt_set_min_eq_max is
also moved out as a part of the above function.

Also add a branch coverage for the case when g->disable_syncpoints is
set to true.

Jira NVGPU-913

Change-Id: I2512d01e105551732aad63b2800bb4cb6d913cb2
Signed-off-by: ddutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263003
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Seeta Rama Raju
3c1a6d1e32 gpu: nvgpu: remove fault injection variable 
- we removed support of "nvgpu_nvrmread_get_fault_injection" function,
  no long this variable required.

JIRA NVGPU-4452

Change-Id: I6add5158e05da4bb571177404ab059e675de21cd
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261838
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 2020-12-15 14:10:29 -06:00
Antony Clince Alex
81720e81fa nvgpu: userspace: update tests to use mock-iospace library 
Remove mocked IO space definitions from units like fifo and gr, instead
get these from mock-iospace library.

Jira: NVGPU-4520

Change-Id: I397e0bccdb4f744d9dd7fb57d2a2a504abcc618b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261826
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
9a89b94a68 gpu: nvgpu: falcon: fix test_falcon_bootstrap 
After hs_ucode_bootstrap the PMU falcon registers were being checked
incorrectly. Fix the logic and update the register offsets with that
of GPCCS registers.

JIRA NVGPU-2214

Change-Id: Ic28cd8eb6894fc16418434a95e46f81095861892
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261166
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Antony Clince Alex
8ffbd7faff nvgpu: userspace: bundle mocked IO space definitions into library 
At present each nvgpu test unit defines its own mocked IO space. This is used to
intialize the qnx/posix IO framework. This results in unwanted redefinitions,
bloating of the binary. This patch creates a shared library which contains all
the mocked IO space definitions and it exports a function which enable units to
query, get access to the mocked IO space.

Jira: NVGPU-4520

Change-Id: Ied19f14e25274953e15a785b3a73053d84012b80
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260042
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
b1e4c0ef72 gpu: nvgpu: falcon: add unit tests for branch coverage 
Add test case to cover gk20a_is_falcon_idle branches, non-word multiple
copy cases in copy to imem and dmem, buffering logic in unaligned data
copy to imem/dmem.

Also update falcon_copy_to_dmem|imem_unaligned_src logic to compare the
offset with size.

JIRA NVGPU-2214

Change-Id: Ib891dc57f36a66818837f951c4453588b71fed90
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259146
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
70f614e07e gpu: nvgpu: falcon: add boundary value test for copy to memory 
Copy to falcon's IMEM and DMEM begins at offset that lies between 0 and
(IMEM/DMEM size - 1). Hence update the validation check. Add the test
case with offset set to the size of IMEM/DMEM that covers all branches
in the function falcon_memcpy_params_check.

JIRA NVGPU-2214

Change-Id: I4807331302014a1b012aa6c05919865b49c86dec
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258312
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
6eef1a486c gpu: nvgpu: falcon: add unit tests and update functions 
Add unit tests to cover the invalid falcon port access, falcon sw init
switch cases, nvgpu_falcon_set_irq, nvgpu_timeout_init failure branch
coverage.

Compile out the functions nvgpu_falcon_get_mem_size & falcon_bootstrap
as they are needed by LS PMU and VBIOS code. For iGPU safety the
falcon functions needing these will call the HAL APIs directly.
This way we avoid the unreachable code as well. Updated the
prototype of falcon bootstrap HAL API as that doesn't return
any error.

With these changes, we get 100% line coverage for common.falcon unit.

JIRA NVGPU-2214

Change-Id: I1fe653d97c1a6a1521d7da38f171928dda58c5b5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258311
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
fba516ffae gpu: nvgpu: enable PMU ECC interrupt early 
PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.

Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.

PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.

Update the doxygen for changed functions.

JIRA NVGPU-4439

Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2251732
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
359fc35fa8 gpu: nvgpu: unit: fifo: runlist unit test 
This unit test covers most of the nvgpu.common.fifo.runlist module lines
and almost all branches.

Jira NVGPU-3699
Jira NVGPU-4135

Change-Id: Ie15579a3c5f7903c2e25ba973078636edea712c9
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2227154
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 2020-12-15 14:10:29 -06:00
Nicolas Benech
533d9e1dc0 gpu: nvgpu: unit: fix crash in handle_bar2_fault test 
In release config, the handle_bar2_fault test was failing. This
was caused by pointers to string not being initialized in the
mmu_fault_info structure.

JIRA NVGPU-932

Change-Id: Ie47f414c3701b851dc175bed19b68d9c9aec87d9
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264181
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
cb117411ca gpu: nvgpu: cg: update the gating reglist hals 
pwr_csb slcg, blcg gating registers are covered by pmu slcg/blcg hence
its load functions are not used. Hence, delete the generated data and
functions. slcg, blcg ctxsw_firmware and pg_gr gating reglists are
null hence delete the generated data and functions.

JIRA NVGPU-2175

Change-Id: Ib04d9845331c9a287666d3b8c974e1d3b66a7677
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263272
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Sagar Kamble
4eca7b806c gpu: nvgpu: cg: load therm unit SLCG gating registers 
Therm unit SLCG hal was not called earlier. Call it from
nvgpu_init_therm_support and add unit tests.

JIRA NVGPU-2175

Change-Id: I158878f4a49e580c7addeff619e0a838020c7987
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263271
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 2020-12-15 14:10:29 -06:00
Scott Long
b93a5a3b6a gpu: nvgpu: fix log doxygen typos 
Fix minor documentation nits in description of nvgpu log apis.

Jira NVGPU-3178

Change-Id: I6d91128cfdf5914b9533bdc4e95d0e6b180fad07
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261443
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
fdb8046812 gpu: nvgpu: unit: add negative tests for common.gr.obj_ctx 
Add negative tests that inject memory allocation failures and
HAL function call errors to verify error handling path in
common.gr.obj_ctx unit.

Update common.gr.setup test to cover invalid class input while
setting preemption mode.

Jira NVGPU-4457

Change-Id: I74d1ba63ba8aace6087b51fd50e2c136822d3a00
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260939
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
34020a5999 gpu: nvgpu: fix issues identified by common.gr.obj_ctx negative testing 
- nvgpu_gr_ctx_load_golden_ctx_image() does not return any error, change
  the return type to void
- Check for preemption modes greater than CILP in
  nvgpu_gr_ctx_check_valid_preemption_mode
- Check if received class is valid or not in
  nvgpu_gr_setup_set_preemption_mode
- Compile out entire nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode since
  it is really not doing anything in safety
- Remove the switch statement in nvgpu_gr_obj_ctx_set_compute_preemption_mode
  since it is not possible to receive any other value than supported.
  Previous function calls ensure that input values are validated.
- nvgpu_gr_obj_ctx_commit_global_ctx_buffers() does not return any
  error, change the return type to void
- gops.gr.init.preemption_state HAL is not needed in safety since it
  only configures gfxp related timeout
- remove redundant call to gops.gr.init.wait_idle in
  nvgpu_gr_obj_ctx_commit_hw_state. We trigger wait despite earlier
  failure in same function call.

Jira NVGPU-4457

Change-Id: I06a474ef7cc1b16fbc3846e0cad1cda6bb2bf2af
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260938
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
71040ef04f gpu: nvgpu: unit: mm: mmu_fault gv11b_fusa UT 
This unit test covers most of the nvgpu.hal.mm.mmu_fault.gv11b_fusa
module lines and almost all branches.

Jira NVGPU-2218

Change-Id: I7c95876a0b1b4bb4b86eb15e21ca0da747d06162
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258545
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 2020-12-15 14:10:29 -06:00
tkudav
8e37e590b4 gpu: nvgpu: unit: unit tests for common.bus 
Add unit tests for common.bus unit.

JIRA NVGPU-928

Change-Id: I0ac146e270890ea703b1a45add7f36c1b08451a5
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258297
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
c404af5575 gpu: nvgpu: unit: mm: hal/gmmu/ unit tests 
This unit test covers most of the nvgpu.hal.gmmu module lines and
almost all branches.

Jira NVGPU-2218

Change-Id: Ibf73a090ec1195b7dc1c8827967f0e7c773228da
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254733
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
f31171a667 gpu: nvgpu: unit: mm: flush_gv11b_fusa unit test 
This unit test covers most of the nvgpu.hal.mm.cache.flush_gv11b_fusa
module lines and almost all branches.

Jira NVGPU-2218

Change-Id: I565cf289079f754d3f76b6680e853d1859c52283
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248383
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
1fa65bcc13 gpu: nvgpu: unit: mm: gp10b_fusa unit test 
This unit test covers most of the nvgpu.hal.mm.gp10b_fusa module lines
and almost all branches.

Jira NVGPU-2218

Change-Id: I16be22aefd10b8a8ee456f33619ecaf28776a072
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248083
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
80e9a7428a gpu: nvgpu: unit: mm: gv11b_fusa unit test 
This unit test covers most of the nvgpu.hal.mm.gv11b_fusa module lines
and almost all branches.

Jira NVGPU-2218

Change-Id: I5f0e766329321d29ef1d22ce1e07264562ca124a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248082
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
13b02091bb gpu: nvgpu: init fbpa ecc before initializing fbpa hw 
fbpa ecc counters need to be allocated before enabling the fbpa irqs.

Bug 200572453

Change-Id: Ifdf31f342bf86cd905bf57dbee654ac5483ee777
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263979
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
dinesh
919e1cf85b nvgpu: nvgpu: Fix for signal handler 
The function BUG() will be called for any error conditions in qnx.
As we need to stop the gpu from further processing, signal need to
be raised.

Change-Id: I99034a4ac772f898f9eec7b324512fb1419fcce6
Signed-off-by: dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243314
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Abdul Salam
4bbed24353 gpu: nvgpu: Remove clk_arb specific calls for clk unit 
Add CONFIG_NVGPU_CLK_ARB for clk_arb specific calls from clk unit.
This will compile out clk_arb specific code from clk unit.

NVGPU-4491

Change-Id: Ie0379b190ae0702f9bab0dfdd1dabbb627e60a3f
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263442
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 2020-12-15 14:10:29 -06:00