Commit Graph

5 Commits

Author SHA1 Message Date
Sagar Kamble
ac3cb4cc53 gpu: nvgpu: consolidate FALCON_ID macros
Same Falcon IDs were defined in acr_lsfm.h with additional
defines. Update definitions in falcon.h and remove from
acr_lsfm.h.

JIRA NVGPU-1459

Change-Id: Id08c7f7a16c36087984a4418ddf7f4921084971a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1964438
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-12-04 22:44:43 -08:00
Philip Elcan
3b5bb8a415 gpu: nvgpu: acr: add casts for MISRA 10.3
This adds casts for cases where the ACR code was violating MISRA Rule
10.3. These are cases where assignments are made to objects of different
size or essential types. In cases where the source could overflow the
case, an assert is included.

JIRA NVGPU-1008

Change-Id: Iea2ce500326e8c482663111a36c5b428825bfd04
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959638
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-30 16:34:38 -08:00
Seema Khowala
ba0d76189e gpu: nvgpu: address alloc_blob_space physically
Add NVGPU_DMA_PHYSICALLY_ADDRESSED flag for blob_space.

Bug 2422486

Change-Id: I44347430ee03b473875d8e49500a08c40ef9194f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1962057
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-30 14:13:47 -08:00
Philip Elcan
d740a9cec6 gpu: nvgpu: acr: cast assignments of sizeof to u32
This change fixes a number of This is a MISRA 10.3 rule violation due to
the implicit casts of sizeof() to u32's. This change adds u32 casts to
each of these violations. This should be safe because a 4GB type size
would be very unlikely in this driver.

JIRA NVGPU-1008

Change-Id: I359cda790278af6e6dfaec8599e2b02c11670fc2
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959428
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-28 14:34:21 -08:00
Terje Bergstrom
f00d9ca1aa gpu: nvgpu: Move pmu HAL files to common/pmu
Move PMU and ACR HAL source code files to live under common/pmu. Also
update the #include paths and delete unnecessary #include dependencies.

JIRA NVGPU-961

Change-Id: I29a220bce6de0a46b6a5fe8ff7f9dc4d67395348
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1935626
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-08 20:04:06 -08:00