The GC-OFF feature shall be available only for selective
dGPUs like Volta, etc. To enable this, add a platform flag
to control GC-OFF feature for a given dGPU.
If GC-OFF is not enabled for a dGPU, EPERM error will be
returned by kernel interfaces.
JIRA NVGPU-1100
Change-Id: Ic9e4492b2bb8916d520e78ecb6a500ccd349b70c
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1923249
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This change adds RDMA supports for tegra iGPU.
1. Cuda Process allocates the memory and passes
the VA and size to the custom kernel driver.
2. The custom kernel driver maps the user allocated
buf and does the DMA to/from it.
3. Only supports iGPU + cudaHostAlloc sysmem
4. Works only for a given process.
5. Address should be sysmem page aligned and size should
be multiple of sysmem page size.
6. The custom kernel driver must register a free_callback when get_page()
function is called.
Bug 200438879
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Change-Id: I43ec45734eb46d30341d0701550206c16e051106
Reviewed-on: https://git-master.nvidia.com/r/1953780
(cherry picked from commit d6278955f6)
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The PMU pstate deinit was invoked part of gpu power off. This frees and clears
the pmgr_pmu struct which causes the pmu remove support to crash when it
tries to access the pmgr_pmu object for freeing up the pmu board objects.
Deferred pstate deinit to nvgpu driver removal as there is no reason for it be
invoked part of prepare poweroff sequence.
JIRA NVGPU-1618
Change-Id: I2eb52000f0732d0abed54946e0843367b119d443
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
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Commit ca611e4d0e (gpu: nvgpu: verify usermode mapping is at least
PAGE_SIZE) was not quite the right thing to do; do_mmap() rounds the
length up to a page boundary anyway, but the length must not be longer
than the size of the usermode region which is 64 KB to avoid leaking
access to other registers.
Bug 2441531
Change-Id: Ib1c88a6725db62c8276b6e8b880631227a4fc8cd
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971339
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
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PMU counters #0 and #4 are used to count total cycles and busy cycles.
These counts are used by podgov to estimate GPU load.
PMU idle intr status register is used to monitor overflow. Overflow
rarely occurs because frequency governor reads and resets the counters
at a high cadence. When overflow occurs, 100% work load is reported to
frequency governor.
Bug 1963732
Change-Id: I046480ebde162e6eda24577932b96cfd91b77c69
Signed-off-by: Peng Liu <pengliu@nvidia.com>
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NVGPU_CTXSW_IOCTL_RING_SETUP can be used to setup a custom ring buffer
and it accepts size via arguments. nvgpu driver will return an error
if size requested is greater than 128 * 4096 but this value is hardcoded
and not exposed anywhere.
Add characteristics field in nvgpu.h to expose this size so that corresponding
nvrm_gpu API can use it.
Bug 2169674
Change-Id: Icf9465d4eec6ba3a307ea9490bd5da563944e4f6
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1967596
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We had to force allocation of physically contiguous memory for
USERD in nvlink case, as a channel's USERD address is computed as
an offset from fifo->userd address, and nvlink bypasses SMMU.
With 4096 channels, it can become difficult to allocate 2MB of
physically contiguous sysmem for USERD on a busy system.
PBDMA does not require any sort of packing or contiguous USERD
allocation, as each channel has a direct pointer to that channel's
512B USERD region. When BAR1 is supported we only need the GPU VAs
to be contiguous, to setup the BAR1 inst block.
- Add slab allocator for USERD.
- Slabs are allocated in SYSMEM, using PAGE_SIZE for slab size.
- Contiguous channels share the same page (16 channels per slab).
- ch->userd_mem points to related nvgpu_mem descriptor
- ch->userd_offset is the offset from the beginning of the slab
- Pre-allocate GPU VAs for the whole BAR1
- Add g->ops.mm.bar1_map() method
- gk20a_mm_bar1_map() uses fixed mapping in BAR1 region
- vgpu_mm_bar1_map() passes the offset in TEGRA_VGPU_CMD_MAP_BAR1
- TEGRA_VGPU_CMD_MAP_BAR1 is called for each slab.
Bug 2422486
Bug 200474793
Change-Id: I202699fe55a454c1fc6d969e7b6196a46256d704
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959032
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Add separate new unit gr/ctxsw_prog that provides interface to access
h/w header files hw_ctxsw_prog_*.h
Add below chip specific files that access above h/w unit and provide
interface through g->ops.gr.ctxsw_prog.*() HAL for rest of the units
common/gr/ctxsw_prog/ctxsw_prog_gm20b.c
common/gr/ctxsw_prog/ctxsw_prog_gp10b.c
common/gr/ctxsw_prog/ctxsw_prog_gv11b.c
Remove all the h/w header includes from rest of the units and code.
Remove direct calls to h/w headers ctxsw_prog_*() and use HALs
g->ops.gr.ctxsw_prog.*() instead
In gr_gk20a_find_priv_offset_in_ext_buffer(), h/w header
ctxsw_prog_extended_num_smpc_quadrants_v() is only defined on gk20a
And since we don't support gk20a remove corresponding code
Add missing h/w header ctxsw_prog_main_image_pm_mode_ctxsw_f() for
some chips
Add new h/w header ctxsw_prog_gpccs_header_stride_v()
Jira NVGPU-1526
Change-Id: I170f5c0da26ada833f94f5479ff299c0db56a732
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966111
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This is part of a move to 64KiB for usermode mapping to fix failures
when the system page size is 64KiB. When remapping or zapping the
vma, use the existing size, not hardcoded size. Also change the
verification of the size when creating the mapping to verify it is at
least as big as PAGE_SIZE. This allows 4KiB mappings to continue to
work until nvrm_gpu is changed to use 64KiB mappings.
Bug 2441531
Change-Id: I447ef8e9f84e6d70bbe96b527e267ec41c5630b8
Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1964687
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With MSI enabled and kernel 4.14, there are some occurrences of
interrupts not being launched (no issue on kernel 4.9). If
an interrupt is not served for a software method, we end up most
of the time with PBDMA busy, while engine is idle.
Disable MSI for dGPU on kernel 4.14
Bug 200460636
Change-Id: I3c5657d63195de5c714f44d331ac992199811d9f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968073
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Add a flag that let's userspace enable the unified VM functionality
on a selective bassis. This feature is working for all cases except
a single MODS trace. This will allow test coverage to be selectively
added in certain userspace tests as well to help prevent this feature
from bit rotting (as it has historically done).
Also update the unit test for the page table management in the GMMU
to reflect this new flag. It's been set to false since the target
platform for safety is currently not using unified address spaces.
Bug 200438879
Change-Id: Ibe005472910d1668e8372754be8dd792773f9d8c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951864
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NVGPU_GPU_IOCTL_GET_EVENT_FD should return -EINVAL when invoked in any
chips which donot have NVGPU_SUPPORT_DEVICE_EVENTS enabled. This is
resulting in an use-after-free error in UBSAN from syzkaller fuzzing
in the nvgpu driver.
Also, as an addon remove the flag clk_arb_events_supported as the
device events check can be made using the flag
NVGPU_SUPPORT_DEVICE_EVENTS.
Bug 200463292
Change-Id: I0ed0217704daa9e401b57a268a30b9f798928e4a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1956070
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Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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gv11b_fifo_preempt_tsg needs to access the runlist_id of the tsg as
well as pass the tsg pointer to other public functions such as
gk20a_fifo_disable_tsg_sched. This qualifies the preempt_tsg to use a
pointer to a struct tsg_gk20a instead of just using the tsgid.
Jira NVGPU-1461
Change-Id: I01fbd2370b5746c2a597a0351e0301b0f7d25175
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
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NVGPU_CTXSW_IOCTL_RING_SETUP is used to setup a ring buffer of custom
size for FECS tracing. It uses size field from its arguments to setup a
user-mapped ring buffer for holding FECS Trace entries.
The value from this field is rounded up to nearest page-size boundary.
This rounded up value is supposed to be returned by the IOCTL (as per
description of the field in nvgpu.h).
That is currently not the case and the IOCTL just returns the same value
as that was passed.
This change fixes this issue by returning updated value.
Bug 200469520
Change-Id: I477aefaede9a4cdba921026466db3fb8fbfd0712
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955337
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Split the nvgpu_sgt code out from the nvgpu_mem code. Although the
two chunks of code are related the SGT code is distinct and as
such should be its own unit. To do this a new source file has been
added - nvgpu_sgt.c - which contains all the nvgpu_sgt common APIs.
These are the facade APIs to abstract the actual details of how any
given nvgpu_sgt is actually implemented.
An abstract unit - nvgpu_sgt_os - was also defined. This unit
exists solely for the nvgpu_sgt unit to call so that the OS
specific nvgpu_sgt_os_create_from_mem() API can be moved from the
common nvgpu_sgt unit. Note this also updates the name of what the
OS specific units are expected to call. Common code may still use
the generic nvgpu_sgt_create_from_mem() API.
JIRA NVGPU-1391
Change-Id: I37f5b2bbf9f84c0fb6bc296c3e04ea13518bd4d0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946012
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Some buffers like userd are physically addressed. If nvlink is
enabled, or device is not iommuable, this requires buffer to be
physically contiguous.
Add NVGPU_DMA_PHYSICALLY_ADDRESSED to identify such buffers, in
order to force physically contiguous allocation, only in above
cases.
Bug 2422486
Change-Id: I6426e23b064904e812e6b33e6d706391648a51ae
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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changes in path because we move the nvhost linux user-interface
from include/linux/ to include/uapi/linux
depends on I2e116dc8f6c33f53c03fb56b923931b6e600b534
Bug 2062672
Change-Id: If2e165852432d5795cf6680cfeb5d4b661fdee74
Signed-off-by: Anuj Gangwar <anujg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1953731
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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions. Also set pointer to NULL when freed.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I21ff1ae93ac7b92a71502f97785252c04964e72f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1954003
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Instead of just the base address of the main register range, store
(also) the base address of usermode area. All regs may not be always
available; on vgpu guests we have only the usermode regs.
Store the usermode addr we get from a platform resource directly in
gv11b_vgpu_probe() for vgpu. In that case the main reg addr is unset.
The base address is computed in gk20a_pm_finalize_poweron() for native
environments; when the reg addr is read from a resource, the chip is
still unknown and as such the HAL op for reading the usermode base
offset is unavailable.
Bug 200145225
Bug 200467197
Change-Id: I8855bb54a6456eb63b69559c84398f7eeaec3513
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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Enable the unified address space config for
o gp10b
o gv11b
gm20b is suffering from a problem in a T214 MODS test. This should
work for the time being in more recent chips. Also this will
increase the soak time these changes get before being released.
Other chips (vGPUs, dGPUs) will (possibly) be enabled at a later
date.
Bug 200105199
Change-Id: I03a6803c6369d89e8a318886fc642b55c5538dd9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951858
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Currently has_timedout variable is protected by wmb at places
where it is being set and there is no correspoding rmb whenever
has_timedout variable is read. This is prone to errors for
concurrent execution. This change is supposed to fix this issue.
Rename has_timedout variable of channel struct to ch_timedout.
Also to avoid rmb every time ch_timedout is read,
ch_timedout_spinlock is added to protect ch_timedout
variable for taking care of concurrent execution.
Bug 2404865
Bug 2092051
Change-Id: I0bee9f50af0a48720aa8b54cbc3af97ef9f6df00
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930935
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MISRA rule 8.3 requires that all declarations of a function
shall use the same parameter names and type qualifiers. There
are cases where the parameter names do not match between
function prototype and declaration. This patch will fix some of
these violations by renaming the prototype parameter.
JIRA NVGPU-847
Change-Id: I980ca7ba8adc853de9c1b6f6c7e7b3e4ac12f88e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926980
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Add a flag to nvgpu_gpu_characteristics to expose FECS tracing capability to
userspace.
This is required for adding nvrm_gpu APIs for CTXSW set of IOCTLs which were
requested in several bugs.
nvrm_gpu APIs would query this flag to check the availability of IOCTLs.
Bug 2169678
Bug 2169677
Bug 2169675
Bug 2169674
Bug 2169673
Bug 2168342
Change-Id: Ie6ba80a4144637546b97fa93baae67b8d0c4d425
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
While linux os code does not need to be MISRA-compliant this
change switches over all memcpy() uses to nvgpu_memcpy()
with appropriate casts applied to maintain consistency within
the nvgpu source base.
JIRA NVGPU-849
Change-Id: I2c21a7845df5709dafa19508c121f8afa27cc4fc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950995
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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I7ced14d6629e033b0ccef3a93a3dbf099e43ba4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: Iafe7d72a6fd31543653e0e10e2d2e552b6c3514b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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clk_gp106.h and clk_gv100.h define conflicting symbols, which prevent
including them both at the same time. One of the conflicting structs
is namemap_cfg, which has different definitions in clk_gp106.h and
include/nvgpu/clk.h.
Move all constants used only by clk_*.c to be defined there, delete
the extra namemap_cfg structure definition, and modify code to cope
with the unified namemap_cfg.
JIRa NVGPU-596
Change-Id: Id68919da4567ec1507eda0cfaa19bf047a7bfc59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945285
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Ifb8cb992a5cb9b04440f162918a8ed2ae17ec928
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822587
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gk20a.c is used only in Linux build. It's in theory common code, but
in practice implements OS specific policies. Also implement
os/posix/gk20a.c to implement gk20a_init_gpu_characteristics(),
gk20a_get() and gk20a_put() which are called from common code.
JIRA NVGPU-596
Change-Id: I6a6079ca6d4c6a225f0dd0e1cd7c439333a704bf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Update the debug crash dump to be clearer, more concise and
avoid many of the misformatting issues that have crept in over
the last couple years.
This also changes the debug prints to move from pr_err() in
the Linux kernel to nvgpu_err(). This makes it easier to
filter all nvgpu messages in a log file with a single grep
command.
Change-Id: I00ca9e6c32da7a79c8f6903a139bf6b43e89618a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1940515
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Originally the order for output was:
1. Dump platform deps (sync-points/host1x stuff)
2. Dump PBDMA status
3. Dump engine status
4. Dump channel status
The updated ordering is:
1. Dump channel status
2. Dump PBDMA status
3. Dump engine status
4. Dump platform deps (sync-points/host1x stuff)
The purpose of this is to put the useful information first and
relegate the less useful info to later in the dump. We naturally
scan downwards and treat stuff at the top as most important.
The end goal is to make the debug dump as useful in as little
time as possible. So instead of making an engineer dig through
a complex jumble of information to find the useful stuff the
hope is that the useful stuff is immediately available.
Change-Id: I9d2b755676b7e5dc2f8949f14dc36f3d337e2a3f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1940514
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This function returns a boolean describing if a given log
mask is enabled for a given GPU. Previously this returned
and int but the bool type is far better suited for this.
Also implement this function in posix, as it may be useful
to have implemented there if any common code chooses to
use this function.
Change-Id: I7382e73df83282763df1bdbccbbb219c9f3e6f1b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1938341
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I957f8ca1fa0eb00928c476960da1e6e420781c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941002
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Reviewed-by: Adeel Raza <araza@nvidia.com>
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