Add a gops_gin struct for handling chip-specific GIN functionality. For
now, it only has the get_intr_ctrl_msg HAL. Each per-unit INTR_CTRL
register holds an opaque 32-bit value that determines how an interrupt
is routed. The layout of this value is determined by GIN. This HAL
allows units to ask GIN how it should program their INTR_CTRL registers.
Jira NVGPU-9217
Change-Id: I18f86e09701634bdb39db6b6e4728cd3595caa02
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839755
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- During nvgpu module unload, the poweroff sequence
will not wait for the ACK from the PMU for the RPCs sent.
- Due to this, rpc_payload struct info will be present
in pmu seq struct.
- This can lead to memory corruption during unload path.
- To avoid this, return a different value for driver shutting
down scenario from fw ack function and based on this return value
free the RPC payload and release the respective pmu sequence struct.
Bug 3789998
Change-Id: I25104828d836ae37e127b40c88209da81754ffb8
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
When a user-domain gets removed, tsg belongs to this also gets removed
and runlist update happens accordingly. If same tsg was submitted to gpu
then updated runlist also needs to re-submit. This works fine with the
existing legacy cases but if GPU is running the shadow domain submitted
by manual mode scheduler and domain belongs to this gets removed then
updated runlist is not being submitted to GPU. This runlist buffer
inconsistency causes mmu fault later.
This change adds a "remove" field in the runlist domain which gets set
to true when runlist update happens for the channel removal. Later
worker thread submit the updated runlist if this flag set to true.
Bug 3884011
Change-Id: I3ce08a5a281e20661915746e70ac0dcd711f3f38
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2838808
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This patch introduces the flag NVGPU_DISABLE_STATIC_POWERGATE. Further,
static pg related initialization APIs have been updated to check whether
this newly added flag is enabled. If this flag is enabled, then static
pg init gets skipped.
JIRA NVGPU-9350
Change-Id: I450b6dd2c541d31fc40fb5540e557b5db730fee2
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2834021
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EPL lib constructor is replaced by NvEplInit() by safety services.
NvGPU, being an EPL user, needs to call NvEplInit before using EPL
API to report errors.
NvEplInit() usage is limited to user space in Linux, so NvGPU is not
expected to call NvEplInit on Linux.
Bug 3863536
Change-Id: I7fc9b33d3443bd39a6367a0c691bddb80b9edb68
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2817245
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The memory leak issue was due to nvgpu_profiler_unbind_context() calling
nvgpu_profiler_pm_resource_release() for all resources which clears the
flag required by nvgpu_profiler_free_pma_stream() to release the memory
for perf_buf instance block.
Fixing this issue by splitting nvgpu_profiler_unbind_context() to release
all the pm resources at a later time separately.
Bug 3510455
Change-Id: Ibab8d071693e600c46f7e7f16575e36e6f62af3c
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2825013
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This patch is required for
- enabling NVGPU driver on OOT by enabling various
configs required.
- replacing new APIs for some deprecated APIs by
guarding with linux version for soc.c.
- CONFIG_TEGRA_HV_MANAGER is enabled by default in OOT kernel,
removing CONFIG_TEGRA_HV_MANAGER check from various places.
Bug 3812973
Change-Id: I07f0b738ca95d4a3996e7f3ee5e895463db0626b
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822434
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Changes
1. Remove dGPU flag dependency on calling gsp sw init on tot.
2. Created Enable flag for gsp scheduler to enable them on ga10b
platforms.
3. Engine config flag is only enabled for dGPU enabled platforms, as gsp
is using engine functions it need to be enabled for all gsp sched
enabled builds.
4. Changes in gsp_sequence_init/de_init where on qnx we are seeing
issues.
NVGPU-9297
Change-Id: Ia4bce85ae8fd2794da1553e9ea418c76845a10ac
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822537
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- As part of mmap call handler mmap_sem is being acquired which is
causing an BUG: scheduling while atomic:. This is happening because
mmap callback gets called with mmap_sem held. The mmap file handler
is called via call_mmap() via mmap_region() via do_mmap(), and the
caller of do_mmap() must hold down_write(¤t->mm->mmap_sem).
To fix this issue removing the mmap_sem locking from nvs mmap handler.
- If remap_vmalloc_range() is used to map the pages to userspace then
allocated pages should be mapped into virtually contiguous space by
passing VM_USERMAP flag to vmap(). Passing VM_USERMAP to vmap() call
if API nvgpu_dma_alloc_flags_sys() is called with flag
NVGPU_DMA_VM_USERMAP_ADDRESS.
Bug 3884011
Change-Id: I64264f6f6e0dd75b1f828dc58355d740e6ef5ccb
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2820781
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Add API to query all memhandles used for pde and pte.
- Some direct pde/pte allocation should also add entry to the pd-cache
full list.
- Add OS API for querying MemServ handle from nvgpu_mem.
- Traverse through all pd-cache partial and full lists to get memhandles
for all pde/pte buffers.
Jira NVGPU-8284
Change-Id: I8e7adf1be1409264d24e17501eb7c32a81950728
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2735657
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Now that we are planning to enable CTRL_FIFO support with NVS,
there is no need for a separate enabled flag for the same.
CTRL_FIFO support is instead determined by the presence of
NVGPU_SUPPORT_NVS enable flag alone.
For non-auto platforms, Control-Fifo can be disabled by restricting
access to /dev/nvsched_ctrl_fifo.
Jira NVGPU-8619
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I9dbec60e5668f38e1460c43800584e88b16a2550
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2814435
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Use CONFIG_KMD_SCHEDULING_WORKER_THREAD instead of
CONFIG_NVS_KMD_BACKEND to remove confusion about the CPU based
KMD scheduling worker thread.
The KMD based scheduling worker thread caters to both Manual Mode
CPU based scheduler as well as Automatic Round Robin CPU based
scheduler.
For the traditional submit path, add correct handling of the
CONFIG_NVS_PRESENT. CPU based worker thread should be part of
CONFIG_NVS_PRESENT. Eventually, when DCONFIG_KMD_SCHEDULING_WORKER_THREAD
is removed, the application must switch to GSP.
Jira NVGPU-8619
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I0886ef3b2e0124b6fe22c2bf0bf7d1fa98039d00
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2810217
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Any corrected or uncorrected error reported by gpu hw
will be seen by nvgpu-mon. nvgpu-mon will raise a devctl call
to notify nvgpu-rm if its a fatal error interrupt.
nvgpu_cic_mon_handle_fatal_intr is the corresponding handler which will
walk through the entire tree structure of interrupts for all the subunits
and enter quiesce state.
Change-Id: I3c00c61a7f2c52ae1920f84ee7dfb65cba6b683d
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2801693
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
