Reduce code complexity of following functions in gr.falcon unit
nvgpu_gr_falcon_load_secure_ctxsw_ucode(complexity : 14 to 5)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create three sub functions from nvgpu_gr_falcon_load_secure_ctxsw_ucode function
Sub functions to do bootstrap during recovery and cold boot
Generalize sec2 and ls_pmu bootstrap to a single function.
gr_falcon_sec2_or_ls_pmu_bootstrap(with complexity : 4)
gr_falcon_recovery_bootstrap(with complexity : 4)
gr_falcon_coldboot_bootstrap(with complexity : 5)
and reduce nvgpu_gr_falcon_load_secure_ctxsw_ucode complexity to 5
Jira NVGPU-3662
Change-Id: I290580572d6c6dac6aa9bbd93b06c84ec3b93637
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165255
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Compile-out non-secure gr falcon boot related code for safety build by
adding non-secure gr falcon related code under following flag:
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
Added nvgpu_gr_falcon_load_ctxsw_ucode and related functions under
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT flag and enabled this flag only
for non-safety builds.
JIRA NVGPU-3741
Change-Id: I817d8a7be6a675eee514faf7bb93f1382c6da5ce
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158935
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Reduce code complexity of following functions in common.gr.intr
nvgpu_gr_intr_stall_isr(complexity : 33)
nvgpu_gr_intr_handle_sm_exception(complexity : 17)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create five sub functions from nvgpu_gr_intr_stall_isr function.
Four of the sub functions based interrupt types.
One sub function for getting the channel information from context
gr_intr_get_channel_from_ctx(complexity : 4)
gr_intr_handle_exception_interrupts(complexity : 11)
This function complexity will reduce with NVGPU_DEBUGGER disable
gr_intr_handle_illegal_interrupts(complexity : 5)
gr_intr_handle_error_interrupts(complexity : 7)
gr_intr_handle_pending_interrupts(complexity : 3)
and reduce nvgpu_gr_intr_stall_isr complexity to 9
Create one sub functions from nvgpu_gr_intr_handle_sm_exception function
One sub function to report back any warp error.
gr_intr_report_warp_error(with complexity : 3)
and reduce nvgpu_gr_intr_handle_sm_exception complexity to 15
This function complexity will reduce with NVGPU_DEBUGGER disable
Jira NVGPU-3662
Change-Id: Ib325d9d8bca6b48766bc8a75f428dceeac495850
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2160578
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This patch adds the support to handle and report graphics related
exceptions to 3LSS. Specifically, it adds the following exceptions:
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_CROP
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_ZROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZCULL
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_SETUP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES0
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES1
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_PE
JIRA NVGPU-3457
Change-Id: Ib24b67ed33ae139317ec85bba3fbb80ba51fd384
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158609
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Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
used.
Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.
Also, change users of ALIGN to pass unsigned types only.
JIRA NVGPU-3515
Jira NVGPU-3411
Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
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Fix MISRA C-2012 Rule 10.3 error in common.gr unit
misra_c_2012_rule_10_3_violation: Implicit conversion of
"!!(gr->ctxsw_disable_count < 0)" from essential type "boolean" to
different or narrower essential type "signed 32-bit int".
Jira NVGPU-3622
Change-Id: I27fb1aa64906242230678dff345307eb0a2d7bdc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140940
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-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files
JIRA NVGPU-3418
Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.
This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.
Jira NVGPU-3476
Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
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Fix CERT INT30-c issue in gr falcon driver replacing
u32 arithmetic operation with nvgpu_safe_add_u32.
Also replaced SZ_256 with 256U to avoid mixed math calculation
with u32 and UL.
JIRA NVGPU-3413
Change-Id: If4f52845a78b7dc0c7936040d759471ba2e5ffc1
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126840
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Hal API g->ops.gr.halt_pipe() is defined in unsafe unit hal.gr.gr
It is called from safe unit, and it calls into API
g->ops.gr.falcon.ctrl_ctxsw() which is also safe
Hence get rid of unsafe API g->ops.gr.halt_pipe().
Caller now directly calls hal.gr.falcon API to halt pipe
Jira NVGPU-3506
Change-Id: I5439cb79431795fc7c22384832cf632d6db03316
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127755
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Trap handling and SM preprocessing is not needed in safety build i.e.
when NVGPU_DEBUGGER is false
Add NVGPU_DEBUGGER flag for all unsafe processing.
In safety build we only report the SM exceptions and return error
so that recovery is triggered
Also add flag for gr_intr_post_bpt_events() since event handling
is not needed in safety build
Jira NVGPU-3506
Change-Id: I660930fdb185b82c0adb612decbfd3d014ce2524
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127754
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Move some interrupt handling hals from hal.gr.gr unit to hal.gr.intr
unit as below
g->ops.gr.intr.set_hww_esr_report_mask()
g->ops.gr.intr.handle_tpc_sm_ecc_exception()
g->ops.gr.intr.get_esr_sm_sel()
g->ops.gr.intr.clear_sm_hww()
g->ops.gr.intr.handle_ssync_hww()
g->ops.gr.intr.log_mme_exception()
g->ops.gr.intr.record_sm_error_state()
g->ops.gr.intr.get_sm_hww_global_esr()
g->ops.gr.intr.get_sm_hww_warp_esr()
g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask()
g->ops.gr.intr.get_sm_hww_warp_esr_pc()
g->ops.gr.intr.tpc_enabled_exceptions()
g->ops.gr.intr.get_ctxsw_checksum_mismatch_mailbox_val()
Rename gv11b_gr_sm_offset() to nvgpu_gr_sm_offset() and move to
common.gr.gr unit
All of above functions and hals will be needed in safety build
Jira NVGPU-3506
Change-Id: I278d528e4b6176b62ff44eb39ef18ef28d37c401
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127753
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This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id
JIRA NVGPU-3516
Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126829
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renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0
JIRA NVGPU-3418
Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.
Jira NVGPU-3237
Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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