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203 Commits

Author SHA1 Message Date
Terje Bergstrom
3cfc020b91 gpu: nvgpu: Write ZBC registers to DSS 
Bug 1567274

Change-Id: Ife98ae512c62bd26450e59338719c7a10635b5dd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601108
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
1e4861a347 gpu: nvgpu: gp10b specific CB callbacks 
Bug 1570662

Change-Id: Icb7e90b1216acfd19bb3027dc9e9844eb08c99d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592101
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Kenneth Adams
16c511220e gpu: nvgpu: t18x, gp10b framework 
This change adds gp10b to the nvgpu build as
well as enabling CMA for buffer allocation.

Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76
Signed-off-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553324
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30