FB fault buffer is enabled on finalize poweron. Disable the buffer
in prepare poweroff. This also eliminates the need to disable
the buffer in fault info mem destroy which otherwise accesses
GPU registers after these are locked in prepare poweroff.
Bug 200427479
Change-Id: I1ca3e6ed4417847731c09b887134f215a2ba331c
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776387
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537754
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: Ic2c7d56e552645f2125d9c60a817967be1e8e765
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533355
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-implement mm ops init_mm_setup_hw
This will also call *fault*setup* that will do s/w and h/w
set up required to get mmu fault info
-implement s/w set up for copying mmu faults
Two shadow fault buffers are pre allocated which will be used to copy
fault info. One for copying from fault snap registers/nonreplayable h/w
fault buffers and one for replay h/w fault buffers
-implement s/w set up for buffering mmu faults
Replayable/Non-replayable fault buffers are mapped in BAR2
virtual/physical address space. These buffers are circular buffers in
terms of address calculation. Currently there are num host channels
buffers
-configure h/w for buffering mmu faults
if s/w set up is successful, configure h/w registers to enable
buffered mode of mmu faults
-if both s/w and h/w set up are successful, enable corresponding
hub interrupts
-implement new ops, fault_info_buf_deinit
This will be called during gk20a_mm_destroy to disable hub intr and
de-allocate shadow fault buf that is used to copy mmu fault info during
mmu fault handling
-implement mm ops remove_bar2_vm
This will also unmap and free fault buffers mapped in BAR2 if fault
buffers were allocated
JIRA GPUT19X-7
JIRA GPUT19X-12
Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1492682
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Included all basic ops for gv11b and updated
sm related functions to include new priv register
addresses.
Bug 1735757
Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1126961
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
