MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gp10b hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: I82575d34c1d73542b93f95759e39d63a291514fb
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829945
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gm20b hw headers
by renaming them to follow the convention, 'NVGPU_HEADER_NAME'.
JIRA NVGPU-1028
Change-Id: I49e4af38b83d54a5814ab3e9246a8af1f1e55fe8
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829976
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gp106 hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: I280aed3ca6d903d95c8fd8261a621591fbe4411e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829942
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gv11b hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: Ifceda60d2fbd33bdb5d05bf1e484819d88dedd1e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829718
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in tu104 hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: Id5f46c5cb50765f178379b23f660f759fa881e9b
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921250
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gk20a hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: Ib14774860a784bf066dd958ae1056ecc0115be71
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829809
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add new separate unit common/perf/cyclestats_snapshot.c and add
corresponding header file include/nvgpu/cyclestats_snapshot.h
This unit is h/w independent and simply calls gops.perf.* HALs
exposed by perf unit to do the h/w configurations
Also remove gv11b/css_gr_gv11b.* files as h/w specific sequence
implemented in them is already moved to perf unit
Rename all cyclestats_snapshot HALs in the form nvgpu_css_*()
Jira NVGPU-1103
Change-Id: I303f6becb313ac918e06c495a5fe299947a1f0b1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1916652
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This patch moves the increment and decrement of the user mapped
buffer count to the insert/remove mapped buffer functions since
this value should only ever change when these functions are called.
Bug 200105199
Change-Id: I5b0a86d00e9e948c48e313153a668eb2e10fca49
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917791
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Add sysfs nodes to manage power of dGPU. Writing
pci dev name to poweroff/poweron sysfs node powers
off/on dGPU.
The format of pci dev name is DDDD:BB:DD.F i.e.
domain:bus:device.function
echo 0001:01:00.0 > /sys/bus/pci/drivers/nvgpu/poweroff
echo 0001:01:00.0 > /sys/bus/pci/drivers/nvgpu/poweron
The permissions of nodes are set such that only root
user can write to the sysfs node to control dGPU power
state.
JIRA NVGPU-1100
Change-Id: I904881cab58c5f553e94510a3a10000194238433
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1749848
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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The power rail of dGPU is managed with help of a set of
GPIOs. Using those GPIOs add an interface to power off and
power on dGPU.
Before dGPU is powered off, new work is blocked by setting
NVGPU_DRIVER_IS_DYING and current jobs are allowed to finish
by waiting for gpu to be idle.
The tegra PCIe controller driver provided APIs
tegra_pcie_attach_controller() and tegra_pcie_detach_controller()
are used to manage PCIe link shutdown, PCIe refclk management
and PCIe rescan.
JIRA NVGPU-1100
Change-Id: Ifae5b81535f40dceca5292a987d3daf6984f3210
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1749847
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We right now acquire rulist_submit_mutex to submit runlist and also
to wait for submit completion
But locking is only needed to atomically configure the runlist submit
registers, hence move the locking to inside of
gk20a_fifo_runlist_hw_submit() where we program the registers
Also convert the mutex to spinlock at the same time
Note that similar locking is not required for
tu104_fifo_runlist_hw_submit() since the runlist submit registers
are per-runlist beginning Turing
Bug 200452543
Change-Id: I53d6179b80cb066466b64c6efa9393e55e381bfc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1919058
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a script to install unit tests on a target jetson board.
The installation consists of copying all the binaries generated
by tmake over to that target board and building a source tree
that matches the nvgpu code.
The reason the systemimage out directory is not used is this
is created by the `image createfs' command during the build
process. This script will work after just a simple `tmm[p]'
Change-Id: I1f2650e666a42c12762ab444159b69ba8fc582f8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850545
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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The nvgpu unit test binary and shim library are built
from nvgpu/userspace. The Makefile.tmk in nvgpu/userspace/src
was not being used for anything it seems.
This also updates the nvgpu/userspace makefile to specify the
dependence on libnvgpu-drv.so.
Change-Id: I24b6682c7ebf84c36ef38923eee96a6277a7083c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850544
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
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The POSIX code does not need to be MISRA complient but any macro
code in the POSIX stuff does get checked by nature of the scanner.
Thus we get a lot of false positives that are annoying.
This change fixes a couple of issues in the BUG() and WARN()
macros: '__' prefixes, missing '{}' in if-conditions, and using
a non-boolean in boolean context.
Change-Id: I064b90c2088ef4ea5093ed456241a98f166008ac
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1816681
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
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Add Turing specific common, unit, hardware header files
Make all the Makefile and Makefile.sources changes to compile
all Turing specific code
Bug 200454999
Change-Id: I62ebff5c078b4b8817fc83ea0e4ee3cfffe668dc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917983
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
We right now submit new runlist and wait for submit to complete in
gk20a_fifo_update_runlist_locked()
It is possible that multiple runlists are being updated in parallel
by multiple threads since the lock taken by parent of
gk20a_fifo_update_runlist_locked() is per-runlist
Note that the concurrent threads would still construct their runlists
into per-runlist buffer
But we still have a race condition while submitting these runlists
to hardware.
With an application that creates and destroys multiple contexts in
parallel this race condition gets realized and we see h/w reporting
an error interrupt NV_PFIFO_INTR_SCHED_ERROR_CODE_BAD_TSG which means
a bad TSG was submitted
Fix this by adding a global lock for runlist submit and wait sequence
This ensures that concurrent threads do not try to submit runlists
to the hardware at the same time
Bug 200452543
Bug 2405416
Change-Id: I2660a2e5d9af1da400e7f865361722dc0914f96f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1851114
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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-Call secured_sec2_start() to start SEC2 RTOS ucode execution
on SEC2 falcon in nvgpu_init_sec2_support() function
-Modified nvgpu_init_pmu_support() to do PMU bootstrap
from SEC2 RTOS by sending command.
-Added function nvgpu_sec2_bootstrap_ls_falcons() to
bootstrap LS falcon by taking falcon id as a parameter &
sending request to SEC2 RTOS with command
NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON.
-Modified method gr_gm20b_load_ctxsw_ucode() to
bootstrap FECS & GPCCS falcons using SEC2 RTOS
in cold boot & recovery path.
-Updated ldr_cfg parameters for SEC2 falcon
-Skip adding PMU ucode details to non-wpr blob preparation
to skip supporting of LS PMU falcon bootstrap.
JIRA NVGPUT-85
Change-Id: I5f6828e2737e247767814014801671327bb34a4e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832363
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-Created sec2_ipc.c to support SEC2 IPC.
-Defined nvgpu_sec2_cmd_post() to send command
to SEC2 RTOS from nvgpu along with dependent
methods like seq acquire/release, validate &
write cmd.
-Defined nvgpu_sec2_process_message() to
process message from SEC2 RTOS & route
to correct handler based on flag.
-Method sec2_process_init_msg() helps fetch
parameters sent from SEC2 RTOS to setup
queue, debug buffer as parameters.
-Created sec2 ops under gops to access
sec2 engine specific HALs.
-Defined nvgpu_sec2_queue_init() init
command & message for SEC2 RTOS using
common falcon queue.
-Made Makefile changes to include sec2_ipc.c for build
JIRA NVGPUT-82
Change-Id: I6e4c2d6ec71aa61a543f34680d1412167c9a8cc6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1828034
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Add separate unit for perfbuf in common/perf/perfbuf.c which does not need to
include any h/w file. This unit will utilize HALs exported by
perf_*.c units for h/w accesses.
Add corresponding header file at include/nvgpu/perfbuf.h
Add new HAL gops.perfbuf with below operations :
gops.perfbuf.perfbuf_enable()
gops.perfbuf.perfbuf_disable()
Remove below debug session specific HALs
gops.dbg_session_ops.perfbuffer_enable()
gops.dbg_session_ops.perfbuffer_disable()
Delete file gv11b/dbg_gpu_gv11b.c since it is no longer needed now as it was
only including perfbuf sequence
Also remove perfbuf sequences from gk20a/dbg_gpu_gk20a.c
Jira NVGPU-1102
Change-Id: I57b87c9f0dcd85784f8002bc92728b6d78a68d98
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1819303
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Add separate unit for perf under common/perf/ to provide accesses to h/w
unit hw_perf_*_.c
Implement below HALs in gm20b and gv11b specific h/w files and set them to
appropriate chips
gops.perf.enable_membuf()
gops.perf.disable_membuf()
gops.perf.membuf_reset_streaming()
gops.perf.get_membuf_pending_bytes()
gops.perf.set_membuf_handled_bytes()
gops.perf.get_membuf_overflow_status()
Jira NVGPU-1102
Change-Id: I161990fdb7283f33c0fb2ab6a8051f4bfc3bb181
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1819302
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