Commit Graph

4968 Commits

Author SHA1 Message Date
Konsta Holtta
4f3647ca32 gpu: nvgpu: protect channel abort with submit lock
Bug 200065789

Change-Id: I59eb93c7929a77cd4de4be40fd7902cd05e536c7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/665655
(cherry-picked from commit 4ee1893926557b01d7058a0a4c1c23e4476d7668)
Reviewed-on: http://git-master/r/668850
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
2015-04-04 15:06:04 -07:00
Konsta Holtta
a9423dd192 gpu: nvgpu: fix list_add_tail in dmabuf state
Fix a memory leak: add the newly created state to the dmabuf priv's
state list, instead of the other way around.

Bug 1594784
Bug 200064154

Change-Id: I939746a254bb8bf4d06de7fcecba06c191da665f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/668758
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
2015-04-04 15:06:03 -07:00
Konsta Holtta
4f0ff67832 gpu: nvgpu: cde: ignore spurious context releases
Gpu channels may get spurious updates from at least nonstalling
semaphore wait interrupts. Protect data structure sanity by ignoring
releases on already released (= not in use) cde contexts.

Bug 200062826

Change-Id: I5940a7557e902bcfcff1a7e8e4593472d9ac306c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/666235
(cherry picked from commit 47dc2f41eb8054b099b6eb9a4a7d82c97295d415)
Reviewed-on: http://git-master/r/666657
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
2015-04-04 15:05:33 -07:00
Ishan Mittal
4284b5edc0 gpu: gk20a: Removing erroneous increment statement
This must have occurred while rebasing dev-kernel-3.10
over kernel 3.18.
This change corrects the mistake.

Change-Id: I11fbc11105a032198828e8bc31da5ab92af0ffdb
Signed-off-by: Ishan Mittal <imittal@nvidia.com>
Reviewed-on: http://git-master/r/720240
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2015-03-20 02:32:07 -07:00
Dan Willemsen
b53b2973fe gpu: nvgpu: Fix/HACK for v3.18
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2015-03-18 20:19:10 -07:00
Dan Willemsen
6e3d5ac13f host/gpu: Upgrade to new fence-based sync implementation
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2015-03-18 20:19:07 -07:00
Dan Willemsen
e6292247ad gpu: remove devm_request_and_ioremap
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2015-03-18 12:12:37 -07:00
Deepak Nibade
d4b3b74044 gpu: nvgpu: add error prints for do_idle() failure
Add error prints in gk20a_do_idle() to narrow down
the failure point

Bug 200064302

Change-Id: Iffe1151bdc200a79b88e273b3b01523f8e46d130
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/664446
(cherry picked from commit bf1cd9b5551d27cb5cc468795cd147376f48e482)
Reviewed-on: http://git-master/r/666218
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2015-03-18 12:12:35 -07:00
Matt Craighead
235f3a3bce gpu: nvgpu: update regops whitelist
Remove an undesired register from the regops whitelist on both
gk20a and gm20b.

Bug 1589732

Change-Id: I7747fafd3c2c32a9c5ce6388be73c7f61e509f0a
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/663373
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:33 -07:00
Supriya
402bdd57e8 gpu: nvgpu: Send aligned addresses to allocator
Bug 1587090
Bug 200050711

PMU dmem start address is unaligned.
Allocator allocates aligned length amount of memory
But address alloced is nto checked to be aligned, but
free checks for alignment of addresses before free.
For dmem case, frees never actually happened. This fix
ensures addresses are aligned.

Change-Id: I8b95f89940aa4d23355c3788dc95afb5c8867373
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/663140
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:33 -07:00
Terje Bergstrom
0bc513fc46 gpu: nvgpu: Remove gk20a sparse texture & PTE freeing
Remove support for gk20a sparse textures. We're using implementation
from user space, so gk20a code is never invoked.

Also removes ref_cnt for PTEs, so we never free PTEs when unmapping
pages, but only at VM delete time.

Change-Id: I04d7d43d9bff23ee46fd0570ad189faece35dd14
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/663294
2015-03-18 12:12:32 -07:00
Supriya
e462c6a7ad nvgpu: gm20b: Ensure ACR boot failure is returned
Bug 200059877

ACR boot failure is returned in falcon mailbox 0
return EAGAIN in case of ACR boot failure

Change-Id: I683984402137bb42dd69f2d667191d5986144c17
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/660529
(cherry picked from commit 404c98b704bec5c707bd0c9b03364c8c6d546cbf)
Reviewed-on: http://git-master/r/662476
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:32 -07:00
Mahantesh Kumbar
e00ec6230d gpu: nvgpu: Added GPMU app version for T18x
Added app version which allows to load & boot T18x GPMU.

Bug 200064127

Change-Id: Iebcfcb984bfbdcd3fb55cf2155c5e75831d5ad95
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/663141
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:32 -07:00
Mahantesh Kumbar
d37aa77ab5 gpu: nvgpu: Allow enabling/disabling MC interrupt
Added method to enable/disable MC interrupt by unit

Bug 200064127

Change-Id: I89e794d5b69a2a93642e2df437d6744bf595f021
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/661211
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:31 -07:00
Konsta Holtta
31f47b8306 gpu: nvgpu: cde: allow duplicate finish signals
Channel update callback for a channel that has no more cde jobs signals
that a cde context is free. Spurious channel updates may still happen
from at least nonstalling semaphore wait interrupts. Instead of scary
WARNs, use only gk20a_dbg_info() for info prints in these harmless
situations, and double check that only the first update starts a deleter
work for temporary contexts.

Change-Id: I68de8f35e2c366206c6efac3ee97025239e8bba2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
(cherry-picked from commit f56a941b4962c5479291cae48e2abca6067e3f13)
Reviewed-on: http://git-master/r/660849
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:31 -07:00
Matt Craighead
d7988e581f gpu: nvgpu: update regops whitelist
Remove an undesired register from the regops whitelist on both
gk20a and gm20b.

Bug 1589712

Change-Id: I76e8ff1f4b68d6d5ce2c11adc08d984df7883e5e
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/663371
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:30 -07:00
Seshendra Gadagottu
666d13757b gpu: nvgpu: gm20b: update regops whitelist
Update regops whitelist ranges with latest script output.

Bug 1500195

Change-Id: I2c61bf068cf81e07f64cbe8a496db7c784a44d8d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/607603
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:28 -07:00
Terje Bergstrom
0d9bb7f82e gpu: nvgpu: Per-chip context creation
Add HAL for context creation, and expose functions that T18x context
creation needs.

Bug 1517461
Bug 1521790
Bug 200063473

Change-Id: I63d1c52594e851570b677184a4585d402125a86d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/660237
2015-03-18 12:12:27 -07:00
Terje Bergstrom
5477d0f4c2 gpu: nvgpu: Generic mem_desc & allocation
Make mem_desc a generic container for buffers. Add functions for
allocating and mapping buffers to an address space which store their
data in mem_desc.

Change-Id: I031643442c6fd41f5e7222fe9b7bfcaf9b784db5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/660908
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2015-03-18 12:12:27 -07:00
Terje Bergstrom
69bb5e1569 gpu: nvgpu: Simplify pagepool size query
Make pagepool size query into a function instead of storing the value
during boot time in a structure. This simplifies the structure and
users of pagepool size do not need to worry about whether it has
already been set.

Change-Id: Iba16e840cdf9b6c39449730237aa7d8fdff47848
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/660907
2015-03-18 12:12:27 -07:00
Matt Craighead
0abb99eb9c nvgpu: gm20b: remove write to RO register
This register has no writeable fields.

Change-Id: I86c132e866c7502a3d0e3a1b8b9942522051992b
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/660956
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2015-03-18 12:12:27 -07:00
Deepak Nibade
d930e24358 gpu: nvgpu: fix sparse warnings
Fix below sparse warnings :
kernel/drivers/gpu/nvgpu/gm20b/mm_gm20b.c:283:5:
warning: symbol 'gm20b_mm_get_big_page_sizes' was not declared.
Should
it be static?
kernel/drivers/gpu/nvgpu/gm20b/clk_gm20b.c:1055:12:
warning: symbol 'gm20b_clk_get' was not declared. Should it be
static?

Bug 200032218

Change-Id: Id199b4b1853b3c933c91509fd550c7b5538cff29
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/660133
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2015-03-18 12:12:27 -07:00
Timo Alho
31a436b3a1 Revert "gpu: nvgpu: Enable syncpt reclaim only on gm20b"
This reverts commit 8eefb93c21934b101d7f423c38d9ea384a45fad6.

Bug 1585422

Change-Id: I217e0ffe6c230ee3c63d9aec1c48ce9c41770468
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/659426
2015-03-18 12:12:26 -07:00
Terje Bergstrom
383f176a9d gpu: nvgpu: Submit coverity fixes
Clear ioctl buffer and fix double free, and error case memory leak.

Bug 200059216

Change-Id: I21cc2b0f6a7e8fca09f72caf4c54d570b13f400b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/655347
2015-03-18 12:12:25 -07:00
Vijayakumar
0fd396a87d gpu: nvgpu: fix coverity issue in pmu logging
bug 200059216

use boolean to return status of hex search
in the string

Change-Id: Ifa53edccf54b9741b369f3a1ab5c79b6aad6cf86
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/656749
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:25 -07:00
Aingara Paramakuru
5bac50c044 gpu: nvgpu: vgpu: debugger interface fixes
To run CUDA apps, the following minimal changes have been
made:
- power-gating is disabled for vgpu
- regop rd/wr returns -ENOSYS

Tools (debugger/profiler) support is known to not work and
not needed at this time.

Bug 200043227

Change-Id: I923caad78450e72d310fb9290cf2849ed5460ad5
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/592878
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:25 -07:00
Terje Bergstrom
3683428235 gpu: nvgpu: Enable syncpt reclaim only on gm20b
gm20b has more channels than sync points. We use aggressive reclaim
of sync points to offset that. Disable aggressive reclaim for gk20a
because it is not needed there.

Bug 1583849

Change-Id: I2a74b0504150a54cb8a97016effe20c5d905ac95
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/657095
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
2015-03-18 12:12:25 -07:00
Vijayakumar
0d11ff0c9c gpu:nvgpu:gm20b: update pg sequencer data
bug 1553301

sequencer data picked up from p4sw #19041893

Change-Id: I3d05972201572e3db31d1b46e93c03dda3e58d54
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/657023
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:23 -07:00
Konsta Holtta
5a181649a7 gpu: nvgpu: cde: remove unused obj_ids
obj_id from gk20a_alloc_obj_ctx is not used and calling free_obj_ctx is
effectively a no-op, since the corresponding channel is also freed.

Bug 200059216

Change-Id: Icbe2cf5dc21d50cb007bf73829705451ada106ac
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/655368
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:22 -07:00
Konsta Holtta
e99b59d14a gpu: nvgpu: add gk20a_scale_exit()
When removing the module, remove the device from devfreq and free
resources allocated when scaling is initialized.

Bug 1476801

Change-Id: I7bb0f8112a5bf7e5ce2fc56cf8af7059d910002c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/594444
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:22 -07:00
Konsta Holtta
6049301229 gpu: nvgpu: remove platform device on exit
Add ->remove() for undoing the ->probe() and ->late_probe() in
gk20a_platform devices, and call it when gk20a is removed.

Bug 1476801

Change-Id: Ic9b29c0a7ea4a4cae7b5a0f66774bd799eb28434
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/594443
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:22 -07:00
Terje Bergstrom
3501269d1c gpu: nvgpu: Export gm20b kind functions
Bug 1567274

Change-Id: I21dadc0e473f174e7ae876b934dcd938bc956453
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/607007
GVS: Gerrit_Virtual_Submit
2015-03-18 12:12:22 -07:00
Konsta Holtta
ddfa305151 gpu: nvgpu: cde: fix off-by-1 in buf allocation
Bug 200046882

Change-Id: I515e972f84cb7e1b17eef42ade6a4eaf0f8d71f8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/559332
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:21 -07:00
Hiroshi Doyu
75af9eb590 gpu: nvgpu: detect iommu'ability dynamically
A device can be iommu'able whenever it's registered so that this patch
detects its iommu'ability dynamically.

Bug 1577389

Change-Id: I8ea20e5dd997fc1a399f517c17783323f238ecc3
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/606019
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:21 -07:00
Terje Bergstrom
8af8c35741 gpu: nvgpu: Implement per-chip pagepool size
Bug 1567274

Change-Id: Ib366f56c109f60be98435124e9e73697d161c4d0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606935
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
2015-03-18 12:12:20 -07:00
Terje Bergstrom
bf9f5f82d1 gpu: nvgpu: Use driver-wide timeout for ACR boot
In simulation we disable timeouts system-wide. Use the system-wide
timeout for ACR boot to enable ACR boot in simulation.

Bug 1546850

Change-Id: I58fc0485725195feab24ae5fe4f249116668bbcc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606273
2015-03-18 12:12:19 -07:00
Terje Bergstrom
2d71d633cf gpu: nvgpu: Physical page bits to be per chip
Retrieve number of physical page bits based on chip.

Bug 1567274

Change-Id: I5a0f6a66be37f2cf720d66b5bdb2b704cd992234
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601700
2015-03-18 12:12:19 -07:00
Konsta Holtta
1deb73b9c6 gpu: nvgpu: clean up module deinitialization
Fix gk20a module removal so that the driver can be correctly removed
when built as a module (CONFIG_GK20A=m). Reinsertion correctly will need
more missing deinit calls, which are not yet implemented.

This change has no effect yet on any builds since the module is built in
by the defconfig.

- don't free threaded irqs that are bound to the device
- destroy cde if it is enabled
- remove all debugfs entries recursively generated directly and by cde,
  pmu, clk etc.
- free secure buffer if it exists
- remove pm_runtime_put, since it doesn't have a pairing get
- pm_runtime defines proper function stubs if it is not enabled, so
  remove ifdefs and query pm_runtime_enabled()
- null and free gk20a only after all deinit has been done

Bug 1476801

Change-Id: I73ad72832bdb501fd7071d6ac68d461ee63a760d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/594442
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:18 -07:00
Alex Frid
b49903b51c dvfs: tegra21: Rename predict interfaces
Renamed predict voltage interfaces to clarify temperature dependencies
accounted for each interface.

Change-Id: Ic76b25a6a8b22f9268d4b3e4186c53b6c3461192
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/562194
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2015-03-18 12:12:18 -07:00
Terje Bergstrom
f6927096e9 gpu: nvgpu: Add HAL for add ZBC color & depth
Turn add ZBC functions into HALs that can be filled per chip.

Bug 1567274

Change-Id: Ic6ef29d3353d4a0079ea0c80f513ffd579fe554f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601109
Reviewed-by: Automatic_Commit_Validation_User
2015-03-18 12:12:17 -07:00
Konsta Holtta
28f4e53e74 gpu: nvgpu: l2 invalidate/flush for off devices
When doing l2 invalidate or l2 flush, first check if the hw is powered
on. If it is not, nothing is done, as there are no hardware registers
available. As a side-effect, this may race so that the hardware stays
unrailgated.

Change-Id: I8bdbfcee3545355435d4ae01476188eb1b8b8817
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/594441
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:17 -07:00
Konsta Holtta
e22d0082ec gpu: nvgpu: cde: wait for ctx deletion before get
Wait for possible temp context deletion to finish properly before
passing contexts around later, to prevent situations where the context
deleter scheduling would have been completed, but running it would not,
and a new one could have been scheduled again. When finished, schedule
the deleter before freeing the context back to use to prevent races.

Warn in impossible situations when these double deletions would happen.

Bug 200054186
Bug 200052943

Change-Id: I23ca0d1081eea77d0e453b9038adc914909b5f48
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/603439
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:16 -07:00
Konsta Holtta
617541236b gpu: nvgpu: cde: combine init and convert passes
CDE context needs to be initialized in the first run using a separate
initialization gpfifo before the actual conversion. To prevent a race
condition, include both of them in a single gpfifo whenever the
initialization is performed.

Bug 200052943

Change-Id: I7eb09a906c0374825df71eba969e4596b94e5ff2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/602888
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:16 -07:00
Konsta Holtta
f73552baea gpu: nvgpu: cde: add trace events for ctx allocs
Trace cde context allocation and deallocation with ftrace.

Bug 200052943

Change-Id: Ieeb625166662971fb3eb3fb29c986fdb6809c10b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/602886
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:15 -07:00
Konsta Holtta
2d7c5e1a5b gpu: nvgpu: cde: warn on double finish and release
Add WARN to conditions that should never happen, to help debugging
any context issues.

Bug 200052943

Change-Id: Ibe2a9507f3a62bb7b2e263ff3ff21a24a092a971
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/602885
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:15 -07:00
Konsta Holtta
cd072a192b gpu: nvgpu: cde: restrict context count
Add an upper limit for cde contexts, and wait for a while if a new
context is queried and the limit has been exceeded. This happens only
under very high load. If the timeout is exceeded, report -EAGAIN.

Change-Id: I1fa47ad6cddf620eae00cea16ecea36cf4151cab
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/601719
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:15 -07:00
Terje Bergstrom
1d9fba8804 gpu: nvgpu: Per-alloc alignment
Change-Id: I8b7e86afb68adf6dd33b05995d0978f42d57e7b7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/554185
GVS: Gerrit_Virtual_Submit
2015-03-18 12:12:15 -07:00
Terje Bergstrom
c0668f05ea gpu: nvgpu: Retrieve intr & reset id from HW
Query interrupt number and reset id from HW. Use the number
from HW when enabling and detecting interrupts.

Bug 200036089
Bug 1567274

Change-Id: If9cb4db79a19dcb193ba7ad9db7081f4fe1ab433
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/600988
2015-03-18 12:12:14 -07:00
Konsta Holtta
3a504842cd gpu: nvgpu: add trace event for channel update
Bug 200052943

Change-Id: Ied6454bbfb5df9ab29497ecbf2aac495f6d89362
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/602887
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:14 -07:00
Konsta Holtta
8d6f5a7529 gpu: nvgpu: cde: report use counts to debugfs
Create debugfs nodes for ctx_count, ctx_usecount and ctx_cont_top.

Change-Id: I1360853b2650d37a96c8adf76368d48d9b457909
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/602860
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:12:13 -07:00