Below functions in common.gr.obj_ctx subunit include unnecessary
asserts to ensure value is not truncated when parsing into U32 size.
nvgpu_gr_obj_ctx_gr_ctx_alloc()
Make use of nvgpu_safe_cast_u64_to_u32() and remove unnecessary
asserts
Jira NVGPU-4778
Change-Id: Ic06c2f4131b3bba35222f7de5441f82ecee6d83d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277158
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Update gr_test_config_get_pes_tpc_mask() to return 0x2F when called
for third time.
There are 2 PES in a GPC. So essentially we want to cover below two
cases
1. pes_tpc_count[pes0][gpc0] > pes_tpc_count[pes1][gpc0]
2. pes_tpc_count[pes0][gpc0] < pes_tpc_count[pes1][gpc0]
Also, run gr_test_diff_gpc_skip_mask() before gr_test_diff_pes_tpc_mask()
so that gpc_skip_mask calculation can generate above two cases first.
Jira NVGPU-4778
Change-Id: I1c34bbc36b0e126d34529725b6c45b59b7e66b67
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277156
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This patch removes dependency between pmu.clk and hal.clk.
Below is the implementation.
*Init the clk domains inside pmu.clk unit.
*Set this in a member variable and send it to hal.clk unit
*Use this to determine the valid clock domains and read the
monitor registers for each valid domains.
*Return the domain with error code.
*With this all the clk domain data is removed from hal.clk and
only pmu.clk uses it as it owns it.
JIRA NVGPU-4491
Change-Id: Ie57b2472cfaacfd2ce43ac7f95702bd95fb8bbaa
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2272416
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To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute on
different hardware resources. This feature proposes modifications
in the software to modify the virtual SM id to TPC mapping across
the mission and redundant contexts. The virtual SM identifier to TPC
mapping is done by nvgpu when setting up the patch context.
The recommendation for the redundant setting is to offset the
assignment by one TPC, and not by one GPC. This will ensure that both
GPC and TPC diversity. The SM and Quadrant diversity will happen
naturally. For kernels with few CTAs, the diversity is guaranteed
to be 100%. In case of completely random CTA allocation,
e.g. large number of CTAs in the waiting queue, the diversity is
1 - 1/#SM, or 87.5% for GV11B, 97.9% for TU104.
Added NvGpu CFLAGS to enable/disable the SM diversity support
"CONFIG_NVGPU_SM_DIVERSITY".
This support is only enabled on gv11b and tu104 QNX non safety build.
JIRA NVGPU-4685
Change-Id: I8e3eaa72d8cf7aff97f61e4c2abd10b2afe0fe8b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268026
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
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test_gv11b_tsg_bind_channel_eng_method_buffers was missing
in the list of tests for the module.
Added the test, and fixed couple issues:
- wrong test on gpu_va in valid case.
- NULL pointer assignment during test setup, when
tsg->eng_method_buffers is NULL.
Jira NVGPU-4673
Change-Id: I2478425f0380540e8295325ffd3df672dc5d9fd0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276068
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Add the following cases:
- timeout == 0 in gm20b_pbdma_acquire_val
- 32-bit overflow in pbdma_method1_r computation.
Note: 32-bit overflow for pbdma_method0_r in
gm20b_pbdma_is_sw_method_subch is hindered by overflow
in pbdma_method1_r which occurs first.
Jira NVGPU-4673
Change-Id: If8202a4397115efb5af490b1ce974b43699e15c6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276051
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When generating Doxygen XML, if an inner structure is anonymous, the
generated XML will remove the inner structure and merge its members
with the parent structure. This is not ideal for tooling, so this
patch adds a name to a few anonymous structures.
JIRA NVGPU-3510
Change-Id: I42556a6b2a2f9a156d9a74fa894197c845656adc
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274706
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Test case test_gr_setup_set_preemption_mode emulates user mode sequence
to set the preemption mode once after creating the context. This test is
used to show that there is no race or deadlock involved while setting
the preemption mode from user space.
This test is used to prove one of the action coming from FMEA of
common.gr unit. Hence update the test type to include "Safety".
Jira NVGPU-4125
Change-Id: I3153772dfe790e6e4dba99dd94fbfd40c9d6f129
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274968
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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nvgpu_engine_get_gr_runlist_id gets the first instance of
active GR engine using nvgpu_engine_get_ids. Therefore the
engine_id is already known to be valid.
Remove call to nvgpu_engine_get_active_eng_info (which iterates
all engines), and fetch f->engine_info[engine_id] instead.
Also remove non-NULL test for engine_info, which could not
be true.
Jira NVGPU-4511
Change-Id: Ifcc0851e3d14d862e2ed7b21ea57f17a66eca9dd
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263617
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The unit test files for common.ecc unit was not included in the doxygen
source file list, causing them not be parsed by doxygen. Updated doxygen
source list to include them.
Fixed doxyen targets tag for unit test functions within common.ecc unit.
Jira: NVGPU-4819
Change-Id: Idacf3d4d5f297950255c47b6380386be88fbd606
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274725
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event_id_list and event_id_list_locks fields are only
needed in nvgpu_tsg when CONFIG_NVGPU_CHANNEL_TSG_CONTROL
is defined.
Conditionally compile those fields and related code,
so that they are removed from safety build.
Jira NVGPU-4376
Change-Id: I8678aa1b8cd4166aa37bcb42cda1eb9c703fd32f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2273261
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MISRA Advisory Directive 4.5 states that identifiers in the same
name space with overlapping visibility should be typographically
unambiguous.
The presence of both the roundup(x,y) and round_up(x,y) macros in
the posix utils.h header incurs a violation of this rule.
These macros were added to keep in sync with the linux kernel variants.
However, there is a key distinction between how these two macros
work in the linux kernel; roundup(x,y) can handle any y alignment while
round_up(x,y) is intended to work only when y is a power-of-two.
Passing a non-power-of-two alignment to round_up(x,y) results in an
incorrect value being returned (silently).
Because all current uses of roundup(x,y) and round_up(x,y) in
nvgpu specify a y value that is a power-of-two and the underlying
posix macro implementations assume as much, it is best to remove
roundup(x,y) from nvgpu altogether to avoid any confusion.
So this change converts all uses of roundup(x,y) to round_up(x,y).
Jira NVGPU-3178
Change-Id: I0ee974d3e088fa704e251a38f6b7ada5a7600aec
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2271385
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