Add negative tests that inject memory allocation failures and
HAL function call errors to verify error handling path in
common.gr.obj_ctx unit.
Update common.gr.setup test to cover invalid class input while
setting preemption mode.
Jira NVGPU-4457
Change-Id: I74d1ba63ba8aace6087b51fd50e2c136822d3a00
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260939
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- nvgpu_gr_ctx_load_golden_ctx_image() does not return any error, change
the return type to void
- Check for preemption modes greater than CILP in
nvgpu_gr_ctx_check_valid_preemption_mode
- Check if received class is valid or not in
nvgpu_gr_setup_set_preemption_mode
- Compile out entire nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode since
it is really not doing anything in safety
- Remove the switch statement in nvgpu_gr_obj_ctx_set_compute_preemption_mode
since it is not possible to receive any other value than supported.
Previous function calls ensure that input values are validated.
- nvgpu_gr_obj_ctx_commit_global_ctx_buffers() does not return any
error, change the return type to void
- gops.gr.init.preemption_state HAL is not needed in safety since it
only configures gfxp related timeout
- remove redundant call to gops.gr.init.wait_idle in
nvgpu_gr_obj_ctx_commit_hw_state. We trigger wait despite earlier
failure in same function call.
Jira NVGPU-4457
Change-Id: I06a474ef7cc1b16fbc3846e0cad1cda6bb2bf2af
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260938
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Split GR ECC initialization into GPC/TPC and FECS ECC init as FECS ECC
errors during acr_construct_execute need to be reported and handled
hence FECS ECC counters are required to be initialized before
acr_construct_execute.
GPC/TPC ECC counters are dependent on the GR config that will be
initialized only after acr_construct_execute.
nvgpu_gr_intr_init_support is moved to nvgpu_gr_prepare_sw.
FECS ECC interrupt is enabled by default hence interrupt is not
enabled through gr_fecs_host_int_enable_r in nvgpu_gr_prepare_sw.
JIRA NVGPU-4439
Change-Id: Ifc9912f0578015a6ba1e9d38765c42633632b15f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261987
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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get_gpc_mask hal is set only for tu104. Add CONFIG_NVGPU_DGPU check
in the code for using that hal.
gr_config_alloc_struct_mem function is called from nvgpu_gr_config_init
gr_config_free_mem is called gr_config_alloc_struct_mem on failure.
No need to call gr_config_free_mem from nvgpu_gr_config_init again
for failure.
nvgpu_gr_config_init allocate nvgpu_gr_config struct.
config->sm_to_cluster will never get allocated before.So no need to
check for config->sm_to_cluster and do a memset.
Jira NVGPU-4531
Change-Id: I928041c110019bec885f9d5b6978db3032bc493c
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262229
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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handle_tex_exception hal is not set for safety build. Add
CONFIG_NVGPU_HAL_NON_FUSA checking for that hal.
log_mme_exception hal is supported only for turing. Add
CONFIG_NVGPU_DGPU checking for that hal.
gr_intr_handle_class_error always return -EINVAL. Change the
return as void to avoid unwanted error checking.
nvgpu_gr_intr_get_channel_from_ctx function parameter curr_tsgid will
never be NULL based on the current call. Remove unwanted
(curr_tsgid != NULL) check from this function.
Jira NVGPU-4454
Change-Id: I165d1cc5f9e308dfb11d905b59151b44f63a31bb
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259763
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The cond unit test was using native pthreads for threads. This change
updates the posix-cond unit test to use the nvgpu_threads interface to
create threads. This ensures the fault injection is setup correctly in
the threads used in the test.
JIRA NVGPU-2224
Change-Id: I94067d25d109cf0569e0c9d83825fefbfc36701a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258704
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Compile out the function mc_gp10b_log_pending_intrs() with the
CONFIG_NVGPU_NON_FUSA macro since it isn't used in the FUSA build.
JIRA NVGPU-2224
Change-Id: I5b2d465142be7d1bddf114c7374ced7b297c33d0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2257127
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add coverage for the following APIs in the common.sync.syncpt unit.
nvgpu_channel_sync_to_syncpt
nvgpu_channel_sync_get_syncpt_id
nvgpu_channel_sync_get_syncpt_address
In the test "test_sync_create_fail" the branch syncpt_ro_map_gpu_va_fail
wasn't working correctly. This patch adds a change that makes it
execute correctly.
Jira NVGPU-913
Change-Id: I5551e49ebd9567d0b4866fada494eec300893f6a
Signed-off-by: ddutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259898
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Currently, GPU fifo sw_ready flag is not reset after fifo clean_up
execution. This patch resets g->fifo.sw_ready flag in
nvgpu_fifo_cleanup_sw_common() to indicate fifo attributes are reset.
Also, pbdma setup and cleanup functions are optional and may not be
populated. This patch modifies nvgpu_fifo_cleanup_sw_common() to
executes nvgpu_pbdma_cleanup_sw() if pbdma.cleanup_sw is populated.
Jira NVGPU-4339
Change-Id: I6fd53577afdd0a15c75f15b54a916e70e850d1b0
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2237809
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- The only sysfs node supported on safety build
was "/dev/gpu_powered_on".
- In QNX, GPU is always powered on. So, this sysfs node doesn't
convey any extra info. Hence, this patch removes sysfs from safety
build.
Bug 200573132
Change-Id: If5f2a6ac81eefb28e71fb919843328cbe87e417c
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256767
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Compile out unused code in gr.falcon for safety build.
By default NVGPU_SEC_SECUREGPCCS is enabled in Safety build. Add
CONFIG_NVGU_GR_FALCON_NON_SECURE_BOOT checking with non secure code.
In gm20b_gr_falcon_wait_ctxsw_ready function watchdog timer value is
calculated based on clock rate, not needed for safety code.
Add CONFIG_NVGPU_HAL_NON_FUSE checking for unused code in that function.
gm20b_gr_falcon_gr_code_less_equal is the last op status we check.
SKIP or any other status following this will be failed in checking
for valid op status. So code reaching this function mean it is for
only for GR_IS_UCODE_OP_LESSER_EQUAL. So removing the checking for
opc_status != GR_IS_UCODE_OP_LESSER_EQUAL in this function
Jira NVGPU-4453
Change-Id: I156cac59f52779fa7f78052c1f0115d0e8f03bf9
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258768
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Minion Ucode is enabling HS Ucode Encyrption. Minion Ucode builds
will put out separate Debug-signed and Prod-signed Encrypted image
files. The driver will load prod image or debug image depending
on the setting of DEBUG fuse setting.
Add support to read the SCP_CTL_STAT register to differentiate
debug and prod boards and load correct binary accordingly.
Update the binary name to support two minion ucodes binaries in
the build.
JIRA NVLINK-283
Bug 2701677
Change-Id: I5348e9705708eeab4ce639b0721f10882d8970a7
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258097
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add negative tests that inject memory allocation failures and verify
error handling path in common.gr.ctx unit.
Update common.gr.global_ctx unit test to check if global context
buffers are ready after allocation call.
Jira NVGPU-4373
Change-Id: Ia373441819257890f9f10667e6e2e363081a6757
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259074
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