Commit Graph

13 Commits

Author SHA1 Message Date
Vedashree Vidwans
e9e9ae9b92 gpu: nvgpu: fix MISRA rule 14.2 for loops
MISRA Rule 14.2 requires for loop to be well-formed. A well-formed for
loop has below requirements:
1. first clause can be empty or should assign value to a single loop
counter
2. second clause should exist and use loop counter or loop control flag.
It should not use any variable modified in the loop body.
3. third cluase should only update loop counter and should not use
objects modified in the loop body.

This modifies for loops to process single loop counter. The patch moves
additional initializations before for loop, conditions at loop start
and variable updates at the end of for loop.

Jira NVGPU-855

Change-Id: I93ccf1ac0677ff355364a718d2d953467f1d9d95
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108188
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-07 11:37:29 -07:00
Vedashree Vidwans
c90fcbae2a gpu: nvgpu: fix MISRA Rule 2.2 no dead code
MISRA rule 2.2 defines dead code as "operations which are executed but
removal of these operations has no effect on program behavior".
Variable initializations violate this rule if initialized value is not
used and replaced.

This patch fixes some of these reported violations.

Jira NVGPU-858

Change-Id: I694517ace8884c78c63f6346e455078d19b70b4d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110459
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-02 15:56:56 -07:00
Sagar Kamble
1262df6d70 gpu: nvgpu: fix misra rule 5.7 violations in pmuif headers
Identifier names used were already used to represent types. Fix those.
for e.g. pwr_channel in nv_pmu_pmgr_pwr_channel_union.
pmu_init_msg identifier name changed to init_msg as that is used to
represent a type.

JIRA NVGPU-3272

Change-Id: I887b66f08df1e00803d872873f6447f563675d44
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108548
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-02 04:18:49 -07:00
Divya Singhatwaria
b368dc48b3 gpu: nvgpu: Re-factor BIOS unit
- Create nvlink_bios.c/.h files to separate out nvlink
  related bios code.
- Create bios_sw_<chip speciific>.c/.h files to separate
  out chips specific bios code.
- Create hal files for bios under hal/bios/ and move
  hardware specific code there.
- Move hardware accessing hal files from common/top
  to hal/top

JIRA NVGPU-2071

Change-Id: Ia466f1cd8947540b07b237e891312123df2c6b46
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107371
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-30 02:47:37 -07:00
Abdul Salam
bc10ef568e gpu: nvgpu: Restructure boardobjgrpmask unit
This patch does the following for boardobjgrpmask unit.
1. Remove unused functions and its pointers.
2. Append public functions with nvgpu.
3. Remove unnecessary inclusion of header files.
4. Make local functions as static.
5. Rename function names to increase readibility.
6. Remove boardobj* from static functions.

Jira NVGPU-1977

Change-Id: Ie6d3bd8f55784d29ae4ba720fb3998487ad2b942
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107167
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-29 11:04:46 -07:00
Sagar Kamble
bcbc87dc2e gpu: nvgpu: move pmu interface headers to include/nvgpu/pmu
Interface header files for PMU features are now moved under PMU header
files directory include/nvgpu/pmu. And fix bulk of coding style issues.
Update header file names and guards.

JIRA NVGPU-1971

Change-Id: Idf53fc09d8928d1b0a1cd16eef886de010dae06b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093006
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-13 12:33:52 -07:00
Sagar Kamble
16953b9622 gpu: nvgpu: prepare pmu command unit
pmu_ipc.c had functionality for rpc response handling and message cond
checks. This patch moves them to msg unit. And prepare cmd.h to group
together structs and functions related PMU commands.

JIRA NVGPU-1970

Change-Id: Iec5d72d02ab3ee51963631c828b301c56af8dc48
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079146
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-05 05:06:22 -07:00
Sagar Kamble
2250ccbe35 gpu: nvgpu: remove seq_desc parameter of pmu callbacks
This parameter isn't used by the callbacks and plan is to keep
access to sequence struct members within IPC units.

JIRA NVGPU-1970

Change-Id: Idcdf4e8f493386be38a5c8a63a741ac06ce1b06e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079140
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-05 05:04:56 -07:00
Sagar Kamble
817e8f28c1 gpu: nvgpu: remove unneeded seq_desc and msg parameter of *_pmu_cmd_post functions
These parameters are not required. Removing those will simplify the
refactoring of the IPC units.

JIRA NVGPU-1970

Change-Id: Id381ba18b87ea21860c05cad1fa64dad8e1a59a1
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079139
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-05 05:04:46 -07:00
Seema Khowala
a8587d5ee3 gpu: nvgpu: rename gr_idle_timeout_default to poll_timeout_default
Rename gr_idle_timeout_default to poll_timeout_default

Rename NVGPU_DEFAULT_GR_IDLE_TIMEOUT to
NVGPU_DEFAULT_POLL_TIMEOUT_MS

Rename gk20a_get_gr_idle_timeout to nvgpu_get_poll_timeout

JIRA NVGPU-1313

Change-Id: I17314f0fa4a386f806f6940073649a9082ee21ad
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083130
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-03-28 16:07:45 -07:00
Philip Elcan
011b42e05f gpu: nvgpu: pmgr: fix MISRA 10.3 violations
Fix MISRA Rule 10.3 violations in common/pmu/pmgr for assigning objects
of different size or essential type.

JIRA NVGPU-1008

Change-Id: Icc6b6757d4231cbad842580b28f5fd86fdb1f79b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027655
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-03-07 11:44:05 -08:00
Philip Elcan
699c2a15fa gpu: nvgpu: pmgr: update type for size param
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.

JIRA NVGPU-1008

Change-Id: I7bff681f04f43e2f599d6f47138b04b2a94bfff3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011436
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-11 14:04:32 -08:00
Terje Bergstrom
dce78f7332 gpu: nvgpu: Move PMU code to common/pmu
Move code interfacing with PMU tasks to common/pmu.

JIRA NVGPU-961

Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950991
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-10 20:09:55 -08:00