vgpu_mm_gp10b files contained gp10b specific code.
- vgpu_gp10b_locked_gmmu_map function is common to all
chips. Rename this function to vgpu_locked_gmmu_map
and move this function implementation to to mm_vgpu
file.
- diable_bigpage variable is set to false in
vgpu_gp10b_init_mm_setup_hw function. This is not related
to mm hw initialization. Move this assignment to
vgpu_init_variables along with other mm specific initialization
as done for native.
Change-Id: I4aba3096a3c945b8b3f4175382ebc78322e1d16e
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2028862
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Create a new directory mm under common vgpu path moving
all vgp common mm files under that directory. This follows
native directory structure.
Move vgpu vm functions from mm_vgpu.c to a new file vm_vgpu.c.
Rename corresponding header file from vm.h to vm_gpu.h
Jira GVSCI-334
Change-Id: Ib77efca0b919478284101894ab16919ba03f71d2
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2013352
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Currently ACR chip specific properties set using HAL ops but
need to move out from HAL ops as ACR unit doesn't access
H/W directly & uses other engines to execute ACR on chip.
To fix used GPUID to init ACR chip specific properties
JIRA NVGPU-2909
Change-Id: I8fa1abcace6f7870bd116d39f94430497d80840b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2032666
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MISRA Rule 10.3 prohibits implicit assignment of objects of narrower
size or essential type. This fixes MISRA 10.3 violations in pmu_fw.c
The API set_pmu_cmdline_args_secure_mode() was updated to accept a u8
for the val parameter to avoid unnecessary casts.
The APIs get_perfmon_cmd_init_offsetofvar() and
get_perfmon_cmd_start_offsetofvar() were updated to pass a u32 by
reference to get the offset value so the return value can be used
properly.
JIRA NVGPU-2841
Change-Id: I8ae34531e843022e8bfa9b5c60ad163b0f7fbf5c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027767
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The following changes are made in this patch.
1) nvgpu driver is incorrectly using u32 to store enum values in some
functions. Replaced them with correct type enum nvgpu_fifo_engine
2) change parameter type in nvgpu_engine_get_ids from engine_id[]
to *engine_ids
3) rename some function names to remove redundant characters to make
the name shorter.
4) Removed the initialization of enum nvgpu_fifo_engine in functions
where we assign a value before direct access.
Jira NVGPU-1315
Change-Id: Ic65b40c9cb1e90ad278cb36a00e1c9de51724f27
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2020230
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Added support to disable/skip to load LS PMU based on PMU support flag,
when LS PMU skipped only basic PMU engine ops are needed for HS ACR
to load & execute on PMU engine falcon,
GR LS falcons cold/recovery bootstrap will be taken care by ACR as HS
ACR will be loaded for both case & exits by halting in non-secure mode.
JIRA NVGPU-173
Change-Id: I7288c185a9ca2e18b2689aa8a7e0c27a61dd12f5
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019927
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA rule 10.6 does not allow assigning of composite expression
to an object with wider essential type. Fix 10.6 violations in nvlink
code by changing the data-type or by type-casting.
JIRA NVGPU-1921
Change-Id: I2d661ca7960e49ebc062c4eb8817004f73297cf5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022881
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FECS trace deinit routine was not checking if tracer was enabled
when attempting to stop the tracer thread. This causes thead stop to
fail when trace is not running.
Jira NVGPU-2801
Change-Id: I09f5eb3c4f498434e6e30394ee675e7745cfde5d
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029941
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The EXPECT_BUG macro is using setjmp/longjmp semantics but was
doing so in an inconsistent way that could cause issues if the
code was compiled with optimizations enabled (release builds).
Specifically, if setjmp is used in an "if" statement, a relational
or equality operator must be used with the right operand being an
integer constant expression. The unary ! operator cannot be used
in this case.
JIRA NVGPU-1246
Change-Id: Iebecff95aefd5b96a8f1f2f13bc178b370374563
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029459
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch ensures that WARN and WARN_ON always return void; and
introduces a new nvgpu_do_assert construct to trigger the equivalent
of WARN_ON(true) so that stack can be dumped (depends on OS support)
JIRA NVGPU-677
Change-Id: Ie2312c5588ceb5b1db825d15a096149b63b69af4
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018706
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- Unify posix lock unit with qnx. Also, fix nvgpu_mutex_trylock return
value. The Linux version expects 1 for success and 0 for failure
whereas posix implementation return 0 for success and negative value
for failure.
Jira NVGPU-1693
Change-Id: I783fb6a82149c096bad17a03e81788bc6b6e1e8c
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003733
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In gr_gk20a_init_gr_config() we right now directly access a register
from hw_pri_ringmaster_*.h h/w header to read FBP count
Add a new HAL operation to PRIV_RING unit and start using it in GR code
instead of directly accessing register
g->ops.priv_ring.get_fbp_count()
Jira NVGPU-2894
Change-Id: I8a7b5423e28ef40612f55cb2915d7a2cff2f7435
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030673
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Below HALs to get max FBPs, max LTC per FBP, max LTS pet LTC values are
right now defined by GR unit.
g->ops.gr.get_max_fbps_count()
g->ops.gr.get_max_ltc_per_fbp()
g->ops.gr.get_max_lts_per_ltc()
These HALs only read registers from hw_top_*.h h/w unit, and as such
belong to TOP unit. Move them appropriately as below
g->ops.top.get_max_fbps_count()
g->ops.top.get_max_ltc_per_fbp()
g->ops.top.get_max_lts_per_ltc()
Remove hw_top_*.h h/w header include from gr_gk20a.c and gr_gm20b.c
Jira NVGPU-2894
Change-Id: I995d9f56edb65c9de98d2d15d34ecb72920a65c6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030672
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Rename gv11b/fecs_trace_gv11b.* files to
common/gr/fecs_trace/fecs_trace_gv11b.*
Also move HAL API gk20a_fecs_trace_get_buffer_full_mailbox_val()
to gr/fecs_trace unit and rename it as
gm20b_fecs_trace_get_buffer_full_mailbox_val()
Protect gm20b/gv11b HAL code under CONFIG_GK20A_CTXSW_TRACE
Remove tu104/fecs_trace_tu104.* since tu104 will re-use gv11b HAL
Fix g->ops.fecs_trace.get_buffer_full_mailbox_val() for vgpu/gv11b and
use gv11b HAL
Jira NVGPU-1880
Change-Id: If78480e36be4e5f0fd659019518f233d8805486d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029259
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Remove below calls from fecs_trace_gk20a.c
gk20a_fecs_trace_ring_read()
gk20a_fecs_trace_poll()
gk20a_fecs_trace_periodic_polling()
gk20a_fecs_trace_reset()
And move them to common gr/fecs_trace unit with below renames
nvgpu_gr_fecs_trace_ring_read()
nvgpu_gr_fecs_trace_poll()
nvgpu_gr_fecs_trace_periodic_polling()
nvgpu_gr_fecs_trace_reset()
Also update above calls to support QNX use cases by adding
vm_update_mask as a parameter
Add below HALs for QNX support. These HALs will not be set for linux
g->ops.fecs_trace.vm_dev_write()
g->ops.fecs_trace.vm_dev_update()
Jira NVGPU-1880
Change-Id: Idc305b9288a1df5ca86622b95d6e62a23fdfde7e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029258
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- rename vgpu_gr_gm20b_init_cyclestats() to vgpu_gr_init_cyclestats()
moving to gr_vgpu.c common to all vgpu chips.
- rename vgpu_gr_gp10b_init_ctxsw_preemption_mode() to
vgpu_gr_init_ctxsw_preemption_mode() moving to ctx_vgpu.c common
to all vgpu chips.
- rename vgpu_gr_gp10b_set_ctxsw_preemption_mode() to
vgpu_gr_set_ctxsw_preemption_mode() moving to ctx_vgpu.c common
to all vgpu chips.
- rename vgpu_gr_gp10b_set_preemption_mode() to
vgpu_gr_set_preemption_mode() moving to ctx_vgpu.c common
to all vgpu chips.
- rename vgpu_gr_gp10b_init_ctx_state() to vgpu_gr_init_ctx_state()
moving to ctx_vgpu.c common to all vgpu chips.
- combine vgpu_gr_gv11b_commit_ins() to vgpu_gr_commit_inst()
executing alloc/free subctx header code only if chip supports
subctx.
- remove inclusion of hw header files from vgpu gr code by
introducing hal ops for the following:
- alloc_global_ctx_buffers:
- hal op for getting global ctx cb buffer
- hal op for getting global ctx pagepool buffer size
- set_ctxsw_preemption_mode:
- hal op for getting ctx spill size
- hal op for getting ctx pagepool size
- hal op for getting ctx betacb size
- hal op for getting ctx attrib cb size
These chip specific function definitions are currently implemented in
chip specific gr files which will need to be moved to hal units.
Also use these hal ops for corresponding functions for native. This
makes gr_gv11b_set_ctxsw_preemption_mode() function redundant. Use
gr_gp10b_set_ctxsw_preemption_mode() for gv11b as well.
Jira GVSCI-334
Change-Id: I60be86f932e555176a972c125e3ea31270e6cba7
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025428
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Create a new directory gr under common vgpu path moving all
vgpu common gr files under that directory.
Move vgpu gr ctx implementations to a new file ctx_vgpu.c
and create corresponding header file.
Also modify parameters of some functions in ctx_vgpu.c to
not access channel/tsg/fifo constructs.
Jira GVSCI-334
Change-Id: I3498b10db62194df2871eb81fc5c5cb04b42abc3
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2013350
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Currently PMU support enable check is done with multiple
methods which added complexity to know status of PMU
support.
Changed to replace multiple methods with support_pmu
flag to know the PMU support, support_pmu will be updated
at init stage based on platform/chip specific settings
to know the PMU support status.
Cleaned up support_pmu flag check with platform specific
PMU members in multiple places & moved check to
public functions
JIRA NVGPU-173
Change-Id: Ief2c64250d1f78e3b054203be56499e4d1d9b046
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024024
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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As a part of regoranizing clk_arb code, This patch does the folowing
1. Move clk_arb HAL files under common/clk_arb unit.
2. Move clk_arb from common/pmu to common/clk_arb.
3. Append public functions with nvgpu.
4. Make local functions as static.
Jira NVGPU-1966
Change-Id: If45c3dbfc4bbe74fe8d30e33e64894d553f3cda5
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027335
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This patch does the following.
1. Append public functions with nvgpu.
2. Move public functions & structure to include/pmu/clk.
3. Remove inclusion of HW header files in common.
4. Move FREQ_STEP_SIZE_MHZ to clk_prog.h as it is used there.
5. Fix 16.3 and 11.3 Misra Violations.
Jira NVGPU-1965
Change-Id: I268d257d6de9c986e456a666cf6d633fe10fc440
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024992
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA rule 14.4 allows only boolean type to be used as controlling
expression in "if" and iteration statement. Replace all non-boolean
expressions with boolean ones in "if" and "while" statements in
nvlink code.
JIRA NVGPU-1921
Change-Id: I8e8b96283c1cadf2c64fc7b8168cf44a6ceb8be5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029073
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Support following changes related to platform atomic feature
NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ
In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege,
so atomic mode register bits cannot be updated from kernel code.
atomic capability and atomic_sys_ncoh_mode bits are copied from
fb mmu_ctrl to gpcs_mmu_ctrl register.
new tu104 hal for fb_enable_nvlink function.
Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2013481
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Add new variable in nvgpu_as_map_buffer_ex_args for app
to specify the platform atomic support for the page.
When platform atomic attribute flag is set, pte memory
aperture is set to be coherent type.
renamed nvgpu_aperture_mask_coh -> nvgpu_aperture_mask_raw
function.
bug 200473147
Change-Id: I18266724dafdc8dfd96a0711f23cf08e23682afc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012679
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Currently a fifo_runlist_info_gk20a structure is allocated and
initialized for each possible runlist. But only a few runlists
are actually used.
Skip allocation and initialization of inactive runlists.
Active runlists info is stored in the active_runlist_info array.
If a runlist is active, then runlist_info[runlist_id] points to
one entry in active_runlist_info. Otherwise, runlist_info[runlist_id]
is NULL.
Operations that used to walk through all runlists are modified to
walk though active runlists only.
Bug 2470115
Change-Id: Icd10281dc904bdee581ebc9cfeb662018ecca121
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025385
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Currently a fifo_runlist_info_gk20a structure is allocated and
initialized for each possible runlist. But only a few runlists
are actually used.
Use an array of pointers to runlists in fifo_gk20a. The array
keeps existing indexing by runlist_id. In this patch a context
is still allocated for each possible runlist, but follow up
patch will allow to skip context allocation for inactive
runlists.
Bug 2470115
Change-Id: I1615043cea84db35a270ade64695d51f85c1193a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025203
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