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Author SHA1 Message Date
Nitin Kumbhar
6208e86ca8 gpu: nvgpu: fix value leaking in log 
The timeout message of nvgpu_timeout_expired_msg() leaks
a stack value (%llx) in error log on timeout. As the format
expects 1 argument and none is given, fix this by specifying
the required argument.

Bug 2626449

Change-Id: I6eddbeaa8b6d91a51d755dfb3df9e7c800f0d161
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205423
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Nitin Kumbhar
f8e4393ace gpu: nvgpu: fix possible buffer overflow issue 
As sprintf() is used to populate pool_name[20], it can overflow
for larger u32 values (u32 max decimal number chars are 10) i.e.
20 < strlen("semaphore_pool-") i.e. 15 + 10.

Fix this overflow by removing pool_name as it's not used.

Bug 2626446

Change-Id: I4e0a222a2cd34dcd09e69294bc46e2242abb04bb
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205356
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
vinodg
f512d17e0b gpu: nvgpu: add definition for shader exception 
Add definition for NVA297_SET_SHADER_EXCEPTIONS_ENABLE_TRUE
Need for gr unit interrupt test

Jira NVGPU-4085

Change-Id: Ia22fae038822e26ecb48369b489d2514b701a84c
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205679
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
vinodg
c9e7f17986 gpu: nvgpu: unit: gr unit test for illegal method 
Add interrupt unit test to handle illegal method
exceptions.

Jira NVGPU-3970

Change-Id: I0ebe7d187100930b40d2263fb390ab2ffe238911
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205034
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
0d30036b30 Revert "gpu: nvgpu: posix: use MISRA-friendly true/false" 
This reverts commit 6db2be854c.

The original commit was to workaround a bug in Coverity that was
misinterpreting "true" and "false" as integers. See nvbug 2623654 for
details on the bug.

Rather than workaround the issue, we whitelist the violations.

JIRA NVGPU-4031

Change-Id: Ie1fe91934aa491966dc960b9706ce1e18d9cf905
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203977
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
7f87599df9 gpu: nvgpu: whitelist MISRA violations due to true/false bug 
Whitelist false positive violations cause by a Coverity bug that
misinterprets "true" and "false" as integers. See nvbug 2623654 for
details on the bug.

JIRA NVGPU-4031

Change-Id: Id144eac1d23be5cfaba73322c3e89c76b5664d6c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203976
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
2a205f6aeb gpu: nvgpu: add whitelisting support for code blocks 
Add additional macros NVGPU_COV_WHITELIST_BLOCK_BEGIN and
NVGPU_COV_WHITELIST_BLOCK_END for whitelisting Coverity MISRA/CERT-C
violation for blocks of code.

JIRA NVGPU-4031

Change-Id: I5dbf5d469903bb446ce8b0258b6d5cab7f7b75d8
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203975
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vinod G
2608c4d80b gpu: nvgpu: ccm fix for gr unit 
Fix CCM issue in gv11b_ecc_init_tpc function
Reduced the complexity below 10 by adding sub functions
in ecc_init for corrected error count and
uncorrected error count.

Jira NVGPU-4084

Change-Id: I27593a68ee80790e9c66168cc1225b3e3a0c27cc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203958
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Thomas Fleury
c00d9f5c8a gpu: nvgpu: unit: add SWUTS docs for nvgpu-runlist 
This adds the SWUTS documentation for nvgpu-runlist unit tests:
- test_tsg_format_gen
- test_flat
- test_flat_oversize_tiny
- test_flat_oversize_single
- test_flat_oversize_onehalf
- test_flat_oversize_two
- test_flat_oversize_end
- test_interleaving_gen_all_run
- test_interleaving_l0
- test_interleaving_l1
- test_interleaving_l2
- test_interleaving_l0_l1
- test_interleaving_l1_l2
- test_interleaving_l0_l2

Jira NVGPU-3943

Change-Id: I569a936346a4726f506d338b54157212529c3be8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202477
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Petlozu Pravareshwar
1e7c3cb038 gpu: nvgpu: add fault injection for posix routines 
This adds the ability to enable fault injection for some of the
POSIX implementation of the nvgpu condition and thread routines.

JIRA NVGPU-2679

Change-Id: I6abb9d5ba3fbe8921e48a135e440c179702dcf6b
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2174647
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vinod G
74723c7f62 gpu: nvgpu: check for non safety code 
Add checking for non safety code to avoid compilation
for safe os.

Jira NVGPU-4085

Change-Id: I7473fb6d97507532e47b7a02b53b6a0771aeb3aa
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204890
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Seshendra Gadagottu
bc83d6aa9c gpu: nvgpu: unit: gr: add gr falcon unit test 
Added following unit tests to cover common gr falcon unit:
gr_falcon_init
gr_falcon_init_ctxsw
gr_falcon_nonsecure_gpccs_init_ctxsw
gr_falcon_recovery_ctxsw
gr_falcon_nonsecure_gpccs_recovery_ctxsw
gr_falcon_query_test
gr_falcon_init_ctx_state
gr_falcon_deinit

JIRA NVGPU-3930

Change-Id: I46f02ac62d8fbdd8704bca34a8088e2de4e2483a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201977
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Divya Singhatwaria
8f1c95f3c3 gpu: nvgpu: ACR unit test 
Add unit tests for ACR unit for the following
function:
nvgpu_acr_init()

JIRA NVGPU-2220

Change-Id: I40c6cf21439e1e9e376230b89cdae6740aec666b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2181677
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Sagar Kamble
ba5d129cfc gpu: nvgpu: address CCM for nvgpu_cg_init_gr_load_gating_prod 
Reduced TCC/MCC below 10 by splitting into BLCG and SLPC load gating
prod functions.

JIRA NVGPU-4101

Change-Id: Ic572e1fe4dd6a3a1edf13d77ddadf08ea2214f74
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205216
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Sagar Kamble
ec293030c1 gpu: nvgpu: move non-safe functions from fusa hal to non-fusa hal 
Multiple non-safe functions under NVGPU_DEBUGGER, NVGPU_CILP and other
config flags were moved to fusa files. Although they are guarded by
the C flags, it makes sense to keep those functions in non-fusa
files. Make this change for all hals.

JIRA NVGPU-3853

Change-Id: I8151b55a60cb50c5058af48bab9e8068f929ac3b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204352
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Rajesh Devaraj
e5259f5819 gpu: nvgpu: add nvgpu_safe_cast_u64_to_u8() 
This patch adds nvgpu_safe_cast_u64_to_u8() since it is required in
SDL error reporting APIs.

JIRA NVGPU-4025

Change-Id: I405b71f61b4c74f8dde51da5f0acd804f0142244
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203707
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Debarshi Dutta
6e2f5a85d3 gpu: nvgpu: rectify incorrect setting of pbdma_acquire_timeout 
The driver was incorrectly setting pbdma_acquire_timeout during default
init when kernelmode submits were disabled. This is corrected to make
the behavior similar to the previous mode. Also, added logging for the
pbdma_acquire_timeout value being set in NV_RAMFC_

Jira NVGPU-3172

Change-Id: Ic39638386bd999871cd8eafec70a3770bc648f93
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203580
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Debarshi Dutta
92a7ea7b01 gpu: nvgpu: remove non-safe code from unit tests 
Remove branch F_CHANNEL_SETUP_BIND_HAS_GPFIFO_MEM from the unit test
for nvgpu_channel_setup_bind as gpfifo_mem belongs to KMD and are not
part of safe builds.

Remove assignment of stub_userd_setup_sw as USERD is compiled out for
safe build.

Jira NVGPU-3172

Change-Id: I4ba72043cb97d8804887c2bed30af9d01dca563e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2142941
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Debarshi Dutta
b2d8c4774f gpu: nvgpu: disable KMDKickoff for safety build 
Disable KMDKickoff for safety builds.

Jira NVPU-3172

Change-Id: I96536066e5bae83179750d4bf15f77e115219ddd
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2142917
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Seema Khowala
96fd5da100 gpu: nvgpu: remove __must_check compiler directive 
MISRA flags all unchecked return values. There is no
need of having __must_check compiler directive.

Also to make sphinx/breathe happy, this is removed.

JIRA NVGPU-3950

Change-Id: I705029de9133feb537ae3712404f311037458bba
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197354
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vinod G
4306faa399 gpu: nvgpu: ccm fix in gr config unit 
Reduce code compleixity in gr_gv100_scg_estimate_perf function
by adding sub functions.

Jira NVGPU-4084

Change-Id: Id12a35aced809b8cfb52ec323eab1d39bfc4cadf
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204038
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Alex Waterman
ec9e8bcbc7 gpu: nvgpu: Use single threaded unit testing 
The parallel unit testing is simply too buggy due to unit tests
not being completely independent. We need to determine exactly
what they are sharing and get rid of that.

For now, force unit tests to run one at a time. This should help
avoid many of the race conditions we see.

Bug 2711887

Change-Id: I04de51998b907d2c2195ea56f6092bbf76ffa1e3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204721
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Joshua Widen <jwiden@nvidia.com>
Tested-by: Joshua Widen <jwiden@nvidia.com>
 2020-12-15 14:05:52 -06:00
Thomas Fleury
f779eb8e9a gpu: nvgpu: unit: use allocated IO reg spaces 
Statically initialized nvgpu_posix_io_reg_space structures are
used in test_fifo_setup_gv11b_reg_space to initialize register spaces.
If fifo, TSG and channel unit tests run concurrently, the same
register space structure can be registered multiple times for
different GPU contexts. This results in list corruption or
use of freed memory.

Use allocated register spaces instead.

Jira NVGPU-3943

Change-Id: I74c080f336e32149d2a378e2b15d37a2bd60ff71
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204062
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
 2020-12-15 14:05:52 -06:00
ajesh
10094b7091 gpu: nvgpu: update SWUT with cond and timers 
Update the SWUT sources and header file to include cond and
timers unit.

Jira NVGPU-3973
Jira NVGPU-3944

Change-Id: I480c6f7558a7e8d13fccba5ba79d65816527c904
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203497
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Mahantesh Kumbar
75fc344540 gpu: nvgpu: PMU unit doxygen documentation 
Add doxygen documentation for nvgpu.common.pmu

JIRA NVGPU-2457

Change-Id: If49643f60d3a5fde597b0a1171884fed48551b4b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201198
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Nicolas Benech
8a923f35a4 gpu: nvgpu: unit: increase test coverage of mm.mm 
This patch increases the test coverage of mm.mm and provide the
corresponding SWUTS document.

JIRA NVGPU-3650

Change-Id: I1f8df4021531b44a165b1953ef3113ea0e87a9f3
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191099
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Nicolas Benech
a8afa823f9 gpu: nvgpu: change nvgpu_init_mm_reset_enable_hw to return void 
The nvgpu_init_mm_reset_enable_hw was always returning 0. This patch
changes it to return void instead which removes some useless error
checking.

JIRA NVGPU-3650

Change-Id: I34ddfb63384f4dbf9e682660f9951c11e5204418
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191098
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vinod G
4f47e36848 gpu: nvgpu: fix misra 4.7 errors in gr unit 
Fix remaining misra 4.7 violations in gr unit
misra_c_2012_directive_4_7_violation: returns error information
is not being checked.

Jira NVGPU-4054

Change-Id: Ia3051e6d55cad73523f2bf7f366c7eb58430c893
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201759
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Rajesh Devaraj
556055b25e gpu: nvgpu: remove a service-id from sdl 
This patch removes the following service-id related to MMU from iGPU SDL:
NVGUARD_SERVICE_IGPU_MMU_SWERR_L1TLB_ECC_UNCORRECTED

JIRA NVGPU-3974

Change-Id: Id350bf7ad95b4e46ce339cbd03a34d2031188041
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2200559
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Debarshi Dutta
a3d21d7127 gpu: nvgpu: change CCM for runlist unit 
1) Reduce CCM for nvgpu_runlist_setup_sw by extracting the mapping between
runlist_info and active_runlist into a separate static function
nvgpu_init_active_runlist_mapping.

nvgpu_runlist_setup_sw:
Previous MCC TCC | Current MCC TCC
         12   12 |          6   6

nvgpu_init_active_runlist_mapping:
Previous MCC TCC | Current MCC TCC
	 N/A N/A |          8   8

2) Reduce CCM for nvgpu_runlist_get_runlists_mask by restructuring the
function.
nvgpu_runlist_get_runlists_mask:
Previous MCC TCC | Current MCC TCC
         11   11 |         10   10

Jira NVGPU-4063

Change-Id: I458df50f15b2c4b2eeae8432a7687b83f9049194
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2200378
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Debarshi Dutta
33eaf3849c gpu: nvgpu: change CCM for hal unit 
1) Reduce CCM for gv11b_fifo_preempt_poll_pbdma and extract partial
code into another static function fifo_preempt_check_tsg_on_pbdma

gv11b_fifo_preempt_poll_pbdma:
Previous MCC TCC | Current MCC TCC
         14   14 |          7   7

fifo_preempt_check_tsg_on_pbdma:
Previous MCC TCC | Current MCC TCC
	 N/A N/A |          9   9

2) Reduce CCM for gv11b_fifo_preempt_poll_eng and extract partial
code into another static function fifo_check_eng_intr_pending.
gv11b_fifo_preempt_poll_eng:
Previous MCC TCC | Current MCC TCC
         16   16 |          8   8

fifo_check_eng_intr_pending:
Previous MCC TCC | Current MCC TCC
         N/A N/A |          10  10

3) Reduce CCM for gm20b_pbdma_handle_intr_0 and extract partial code
into another static function pbdma_get_intr_descs.
gm20b_pbdma_handle_intr_0:
Previous MCC TCC | Current MCC TCC
         11   11 |          10  10

pbdma_get_intr_descs:
Previous MCC TCC | Current MCC TCC
         N/A N/A |           1   1

Jira NVGPU-4063

Change-Id: Ic999cc33db08e5036d7d7d8a19ed323185f4c54b
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201462
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Divya Singhatwaria
ac4520b0f7 gpu: nvgpu: Fix CERT-C violations in ACR unit 
Fixed the CERT-C INT30 and INT31 violations
in the ACR unit using:
nvgpu_safe_add_u32() and  nvgpu_safe_sub_u32()

JIRA NVGPU-4073

Change-Id: I360c8094578c65463e196bbb30e399d0369d0b00
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199438
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Abdul Salam
65ecd7a181 gpu: nvgpu: Remove fixed wait time for change seq completion 
Currently after sending change seq RPC, nvgpu waits for a fixed time
of 20ms.
This CL replaces this with pmu_wait_message_cond, which will return
immediately after getting change seq completion event.
Also added debug fs node to get the change seq execution time.

Bug 200545366

Change-Id: Iba283f65d4949858be9cbff88de4d21a8c92ff81
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202423
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Deepak Nibade
8b575a3fff gpu: nvgpu: fix data structure section in GR doxygen 
common.gr unit exposes couple of data structures for use of common.acr
unit. Add them to "Data Structures" section of GR doxygen.

Jira NVGPU-4028

Change-Id: I580178ab7b0a0e7ef52cb0cbdfaf9a81deba2cec
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201374
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Deepak Nibade
cb110723a5 gpu: nvgpu: doxygen for GR private structures [2/2] 
Add doxygen documentation for private GR structures defined in:
gr/gr_config_priv.h
gr/gr_falcon_priv.h
gr/gr_intr_priv.h
gr/gr_priv.h

Remove "p_va" field from struct nvgpu_ctxsw_ucode_info since it is
unused.

Compile out "pm_ctxsw_image_size" with flag CONFIG_NVGPU_DEBUGGER.
Compile out "preempt_image_size" with flag CONFIG_NVGPU_GRAPHICS.

Replace eUcodeHandshakeInitComplete enum value by macro
FALCON_UCODE_HANDSHAKE_INIT_COMPLETE. And remove enum value
eUcodeHandshakeMethodFinished since it is unused.

Compile "ctxsw_disable_mutex" and "ctxsw_disable_count" in struct
nvgpu_gr only if CONFIG_NVGPU_RECOVERY or CONFIG_NVGPU_DEBUGGER is
defined

Jira NVGPU-4028

Change-Id: Ie8769c1f3f8d313b479b182d3858a6715d49cd4c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201373
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Deepak Nibade
f74506be00 gpu: nvgpu: doxygen for GR private structures [1/2] 
Add doxygen documentation for private GR structures defined in:
gr/ctx_priv.h
gr/global_ctx_priv.h
gr/obj_ctx_priv.h
gr/subctx_priv.h

Compile out struct zcull_ctx_desc with flag CONFIG_NVGPU_GRAPHICS.
Compile out struct pm_ctx_desc with flag CONFIG_NVGPU_DEBUGGER.

Compile out field golden_img_loaded with flag CONFIG_NVGPU_NON_FUSA
since it is only used for VSERVER.

Jira NVGPU-4028

Change-Id: Ic63e751ee28c6b645cc13993b16f701a9dbcf3e0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201372
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Deepak Nibade
99f775b622 gpu: nvgpu: compile out ctxsw stats dump in safety 
CTXSW stats dump is only enabled on Linux and only through DEBUG FS.
Hence add CONFIG_DEBUG_FS compile time flag to remove corresponding
HALs in safety build.

Jira NVGPU-4028

Change-Id: I37088e1572c51ca35b651c56a4cb907eda5c9004
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201371
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Thomas Fleury
d1e6ac0c3e gpu: nvgpu: report only unhandled methods 
Some methods are implemented in SW, and it is expected that
nvgpu driver gets illegal method interrupts for these.
Do not report illegal method error if related method could
be handled. It avoids reporting false errors to 3LSS and
more importantly avoids entering SW quiesce state.

Jira NVGPU-3896

Change-Id: I1e6ddcf20e4038398259d22957619fe7bc2e9c7d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199906
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Thomas Fleury
5a6730de39 gpu: nvgpu: unit: add SWUTS docs for nvgpu-channel 
This adds the SWUTS documentation for nvgpu-channel unit tests:
- test_channel_setup_sw
- test_channel_open
- test_channel_close
- test_channel_setup_bind
- test_channel_alloc_inst
- test_channel_from_inst
- test_channel_enable_disable_tsg

Jira NVGPU-3943

Change-Id: Ibfa1dbf144d3cb2c5836a5b1d1242dd0c35ca2e5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2198892
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Thomas Fleury
bc0ee192e8 gpu: nvgpu: unit: add SWUTS docs for nvgpu-tsg 
This adds the SWUTS documentation for nvgpu-tsg unit tests:
- test_tsg_open
- test_tsg_bind_channel
- test_tsg_unbind_channel
- test_tsg_release
- test_tsg_unbind_channel_check_hw_state
- test_tsg_unbind_channel_check_ctx_reload
- test_tsg_enable
- test_tsg_check_and_get_from_id
- test_tsg_abort
- test_tsg_setup_sw

Jira NVGPU-3943

Change-Id: Ia5222700b0320e03432a6afbbaae26ad2b32d704
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197385
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
920b704ec7 gpu: nvgpu: put memory ref count 
Put dma buffer ref count for all vm buffer mapping fail conditions.

Bug 200531152

Change-Id: I6bfad867eb9bd636a48b5ceb3a4417a80994a3ec
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Original Author: Bruce Xu <brucex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194025
(cherry picked from commit f85504ae46d65d5346d9e2a5cc84ffb960ba9fb7)
Reviewed-on: https://git-master.nvidia.com/r/2195439
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Thomas Fleury
b8df5bcccd gpu: nvgpu: unit: add SWUTS docs for nvgpu-fifo 
This adds the SWUTS documentation for the nvgpu-fifo unit tests:
- test_fifo_init_support
- test_fifo_remove_support

Also added missing register space in remove support.

JIRA NVGPU-3943

Change-Id: I1f3a61cd41af0e8b78b0636adfb3448645e0fc15
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195374
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
vinodg
98495234c7 gpu: nvgpu: unit: gr: Add gr interrupt unit test 
Add test for gr interrupt unit.
This test make gr interrupt isr call, without a channel allocation
and interrupt registers set for all bits.

Jira NVGPU-3970

Change-Id: Ie225663088f35c2cdeb384d9904bff7ebcbac84e
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2200882
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Sunny Li
516023e1e4 gpu: nvgpu: sysfs adding NULL pointer check 
golden image size will be set when memory allocated.
See function:
- nvgpu_gr_obj_ctx_init

If golden image size is 0, gr_golden_image should be a NULL
pointer in most cases. So add NULL pointer checking in
tpc_pg_mask_store to avoid NULL pointer exception.

Bug 2403210

Change-Id: I14df5cd94d7a4418c3089c5f84b6eab93c485ba6
Signed-off-by: Sunny Li <sunnyl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161280
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Deepak Nibade
1d5698cf6a gpu: nvgpu: set GR tick frequency to max 
GR tick frequency needs to be set to MAX value for profiler
use cases for gp10b/gv11b/tu104 chips.

Add new HAL g->ops.ptimer.config_gr_tick_freq() that configures GR
tick frequency to MAX value and call this HAL in GPU poweron path.

This support is not needed in safety build, so compile everything
only if CONFIG_NVGPU_DEBUGGER is enabled

Bug 200289214

Change-Id: Id8378540cc67ca0041b56990f8676e3a105403a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195163
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Sagar Kamble
69f990623b gpu: nvgpu: unit: fix falcon dmemc read logic 
Falcon DMEMC register read returns the bytes copied to DMEM. There was
a mistake in calculating the bytes and setting access->value properly
in falcon utf register read function. Fix it.

JIRA NVGPU-2220

Change-Id: If6ba03f734e27d8d0d027f873b56330c17f7aa0b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201515
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Sagar Kamble
7ee71a4f4b gpu: nvgpu: fix gk20a_falcon_copy_to_dmem return value 
Earlier, gk20a_falcon_copy_to_dmem was not returning failure when bytes
copied as read from dmemc register did not match with expected bytes.
Return error -EIO.

JIRA NVGPU-2220

Change-Id: I168f758c034193db6a13cc3f251b961c7d0095a3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201514
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Mahantesh Kumbar
525ff83910 gpu: nvgpu: Cleanup PMU unit header file pmu.h 
Moved PMU subunits specific defines from pmu.h to
respective subunits header file by renaming properly
as needed

JIRA NVGPU-2457

Change-Id: Id29a2d5cb028fc69049738c735c5585b6276b115
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199547
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Mahantesh Kumbar
5eeb751d58 gpu: nvgpu: Move PMU RTOS functions out from pmu.c 
Moved PMU RTOS functions to new file from pmu.c to make clear
separation of PMU unit init & PMU RTOS init.

JIRA NVGPU-2457

Change-Id: I694bf561517b4b55f9396be8e132dc0da5cb29e6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199543
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Debarshi Dutta
d7ae490dff gpu: nvgpu: Reduce CCM for channel function 
Reduce CCM for nvgpu_channel_suspend_all_serviceable_ch by early
calling channel.unbind

nvgpu_channel_suspend_all_serviceable_ch:
Previous MCC TCC | Current MCC TCC
         11   11 |          8   8

Jira NVGPU-4063

Change-Id: If701c7d83cbde31a19bbc19866962322c58c370d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201486
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00