During finalize power on, resume channels only after
complete hw initialization is done. Otherwise it will
cause issues with unexpected usage of hw. During first
boot will not see these issues because there will no channels.
But after rail gate/ungate or suspend/resume these issues
can be seen if channels are present before rail-gate/suspend.
Bug 2039195
Change-Id: Ie96e2f2b91902ba18b37e9a167344eeae07ba8c2
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1625506
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
In gr_gv11b_set_gpc_tpc_mask(), we calculate tpc_count_mask based on
number of TPCs
But since we could change number of TPCs runtime, we would end up
calulating incorrect tpc_count_mask
Hence instead of calculating tpc_count_mask, just hard code it to
width of fuse register i.e. hard code tpc_count_mask to 4-bit value
Bug 2031635
Change-Id: Ia6f74d39d066775a5d133897305554df1e54157e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1617917
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
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In __nvgpu_gmmu_do_update_page_table(), and in case of non-IOMMU mappings,
we call nvgpu_sgt_get_phys() to get physical address
But this API ignores mapping attributes including l3_alloc attribute
specified by user space, and this breaks L3 cache allocations
Fix this by using g->ops.mm.gpu_phys_addr() which also considers the
mapping attributes and returns appropriate physical address
Jira GPUT19X-10
Bug 200279508
Change-Id: Ibc0d29f7cb576a9d6893a97b1912d9ff4bc78e02
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1621245
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Convert tpc number from pes-aware to non-pes-aware
number. tpc id is converted to one that is numbered
in order starting from the active tpcs within PES0
followed by the active tpcs in subsequent PESs.
Bug 1842197
Change-Id: I18d4b20ee4998e5a2ca5439793fe2479b4326c1a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1615419
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
gr_gv11b_init_fs_state() calls gr_gm20b_init_fs_state() which
disables vdc_4to2. This should no longer be done on gv11b, so
instead of calling gr_gm20b_init_fs_state() copy the relevant
lines to gr_gv11b_init_fs_state() and drop vdc_4to2 disable.
gv11b_ltc_init_fs_state() also disables it to match the state.
Remove that disable, too.
Change-Id: I3a3fd87a3e8836e495cb818570c971b3d29a6dd1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1619966
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Wei Sun <wsun@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
For gv11b, update thermal settings as per hw POR:
1.Created gv11b specific HAL for init_therm_setup_hw
2.Update steps for gradual slowdown to 1x,1.5x,2x,4x,8x,16x,32x.
3.Modified gradual step duration cycles to 4.
Bug 200365110
Change-Id: I93c28a3394857aacdf3d304103c9e7c25d4ad344
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616600
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
All channels should be wrapped in TSGs so that bare channel support
can be dropped. Bind all CE channels to TSGs.
Bug 1842197
Change-Id: Ia55748d5b53750d860f7764b532ef9eeb6f214b8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616693
Check the availability of ecc units by checking
relevant ecc fuse and fuse overrides.
During gpu boot, initialize ecc units by scrubbing
individual ecc units available. ECC initialization
should be done before gr initialization.
Following ecc units are scrubbed:
SM LRF
SM L1 DATA
SM L1 TAG
SM CBU
SM ICACHE
Bug 200339497
Change-Id: I54bf8cc1fce639a9993bf80984dafc28dca0dba3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612734
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nvgpu_get_nvhost_dev will not return error if host1x field within
gv11b device tree is not present. It will just set has_syncpoints
in gk20a struct to false. syncpt_unit_interface* should be called
only if g->has_syncpoints is set to true.
Change-Id: Id1eb94aba4cff1942ad519f528ebdb8291963971
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1615973
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Pre-gv11b we only had 2 TPCs in a GPC. But on gv11b we have 4 TPCs in a GPC.
Hence update gr_gv11b_set_gpc_tpc_mask() as per new configuration and allow
setting bits based on number of TPCs
Bug 2031635
Change-Id: I44f5f6ce5f3e2501c229c9fcda36fb330ebf8bd0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1614044
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GR IDLE timeout is defined as Kconfig. Instead of that introduce a
new header file defaults.h which encapsulates any generic defaults
we use in nvgpu, and move the definition there.
Change-Id: I78ff1d2790d7ee3dff6df42bbd11cf683a85bf79
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612650
GVS: Gerrit_Virtual_Submit
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variable g->gr.ctx_vars.regs_base_index is declared as "int", but it is assigned
value from unsigned int pointer
Since we expect it to be unsigned at all the places, declare it as "u32" instead
of "int"
Jira NVGPU-449
Change-Id: I2a5b35698c655fa0caa3e38e37ed4d84569c996a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612446
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In __gr_gk20a_exec_ctx_ops(), we directly access linux specific pages to check
if memory is allocated or not
Since we need to remove this linux specific dependency from common code,
use common API nvgpu_mem_is_valid() to check if memory is allocated or not
Jira NVGPU-448
Change-Id: Iad62482ad1c0dfad3b96c6c125c2641bbe6ea596
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612445
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gr_gk20a_init_access_map(), we declare num_entries as "unsigned int"
But this variable is implicitly type casted into "int" while calling subsequent
functions
Hence explicitly declare it as type "int"
Also declare variable "w" as "int" too since we use it to compare against
num_entries
Jira NVGPU-446
Change-Id: I289da6951db0a9ed6b8d6bcb3ee4f6071a4ddaf0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612444
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Use NVGPU_DMA_FORCE_CONTIGUOUS for non-wpr blob alloc.
CPU writes some data to non WPR blob (sysmem). ACR binary executing
from PMU, first copies that data to DMEM and then copies that data into WPR.
Without NVGPU_DMA_FORCE_CONTIGUOUS, secure boot fails due to ACR writing
wrong bootloader data to PMU DMEM.
Bug 200355756
Change-Id: I18982caff62b2e7cbe64ea98c1bb935496cfe91c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1610491
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
The current code does not properly calculate the indexes within the PDE
to access the proper entry, and it has a bug in assignement of the big
page entries. This change fixes the issue by:
(1) Passing a pointer to the level structure and dereferencing the
index offset to the next level.
(2) Changing the format of the address.
(3) Ensuring big pages are only selected if their address is set.
Bug 200364599
Change-Id: I46e32560ee341d8cfc08c077282dcb5549d2a140
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1610562
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Bhosale <dbhosale@nvidia.com>
Define __nvgpu_mem_create_from_phys only in systems with nvhost
enabled. The calling code is also built only when nvhost is enabled.
phys_to_page() also exists only in arm64, so using it in non-arm64
platform causes a build failure.
Change-Id: Iee023b55bba863d46079796e1c49c19456c1d229
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607581
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Increase the ctagline that is programmed in the page tables when the
buffer offset crosses the compression page boundaries. This fixes
compressible-kind fixed-address mapping with 4k pages when the GPU VA
is not aligned by the compression page size.
Bug 1995897
Bug 2011640
Bug 2011668
Change-Id: I1f1f9750635a20a916527c9d18fda7f8aa6b1b1f
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1608465
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Add an alignment check for compressible-kind fixed-address
mappings. If we're using page size smaller than the comptag line
coverage window, the GPU VA and the physical buffer offset must be
aligned in respect to that window.
Bug 1995897
Bug 2011640
Bug 2011668
Change-Id: If68043ee2828d54b9398d77553d10d35cc319236
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606439
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Remove linux specific #include "common/linux/os_linux.h" from common source
files gr_gk20a.c/gr_gm20b.c/gr_gp10b.c
Remove use of ZERO_OR_NULL_PTR() and simply check if pointer is NULL or not
Jira NVGPU-405
Change-Id: I663fe298cc720f0b0e22beaa05697b18b375a204
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607233
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For gv11b, configured gfx preemption wfi timeout in usec.
Set timeout unit as usec in gr_gv11b_init_preemption_state.
Used default timeout as 1msec and this timeout value can
be modified through sysfs node:
/sys/devices/gpu.0/gfxp_wfi_timeout_count
For gp10b:
gfxp_wfi_timeout_count is in syclk cycles
For gv11b:
gfxp_wfi_timeout_count is in usec
Bug 2003668
Change-Id: I68d52ce996a83df90b8b3a8164debb07e5cb370f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599658
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