Commit Graph

24 Commits

Author SHA1 Message Date
tkudav
0526e7eaa9 gpu: nvgpu: Create CIC-mon and CIC-rm subunits
common.cic unit is divided into common.cic.mon and common.cic.rm
based on rm and mon process split.

CIC-mon subunit includes the code which is utilized in critical
interrupt handling path like initialization, error detection and
error reporting path. CIC-rm subunit includes the code corresponding
to rest of interrupt handling(like collecting error debug data from
registers) and ISR status management (status of deferred interrupts).

Split the CIC APIs and data-members into above two subunits.

JIRA NVGPU-6899

Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2021-07-02 09:57:56 -07:00
Sagar Kadamati
3e43f92f21 gpu: nvgpu: add ga10b & ga100 sources
Mass copy ga10b & ga100 sources from nvgpu-next repo.
TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1

Jira NVGPU-4771

Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-06-17 12:56:16 -07:00
Tejal Kudav
9f43914933 gpu: nvgpu: Move Intr handling common code to CIC
CIC (Central Interrupt controller) will be responsible for the
interrupt handling. common.cic unit is the placeholder for all
interrupt related code. Move interrupt related defines and
Public APIs present in common.mc to common.cic.
Note: The common.mc interrupts related struct definitions are
not moved as part of this patch.

Adapt the code to use interrupt handling related defines and public
APIs migrated from common.mc to common.cic

JIRA NVGPU-6899

Change-Id: I747e2b556c0dd66d58d74ee5bb36768b9370d276
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2535618
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2021-05-31 19:37:31 -07:00
Rajesh Devaraj
b8c6ad3f5f gpu: nvgpu: remove service IDs
This patch removes the reporting of _ECC_CORRECTED errors which are
not applicable to GV11B. Specifically, this patch removes the code
related to the  reporting of the following service IDs:

NVGUARD_SERVICE_IGPU_SM_SWERR_LRF_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_SM_SWERR_CBU_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_PMU_SWERR_FALCON_DMEM_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_GPCCS_SWERR_FALCON_DMEM_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_FECS_SWERR_FALCON_DMEM_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_GCC_SWERR_L15_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_MMU_SWERR_L1TLB_FA_DATA_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_MMU_SWERR_L1TLB_SA_DATA_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_HUBMMU_SWERR_L2TLB_SA_DATA_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_HUBMMU_SWERR_TLB_SA_DATA_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_HUBMMU_SWERR_PTE_DATA_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_HUBMMU_SWERR_PDE0_DATA_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_SM_SWERR_ICACHE_L0_DATA_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_SM_SWERR_L1_DATA_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_SM_SWERR_ICACHE_L0_PREDECODE_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_SM_SWERR_ICACHE_L1_DATA_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_SM_SWERR_ICACHE_L1_PREDECODE_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_SM_SWERR_L1_TAG_MISS_FIFO_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_SM_SWERR_L1_TAG_S2R_PIXPRF_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_LTC_SWERR_CACHE_TSTG_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_LTC_SWERR_CACHE_RSTG_ECC_CORRECTED
NVGUARD_SERVICE_IGPU_LTC_SWERR_CACHE_DSTG_BE_ECC_CORRECTED

Bug 200616002

Change-Id: I199c396f9f6a6be007bd6d3c556199b5a73c3c91
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2349587
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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2020-12-15 14:13:28 -06:00
Antony Clince Alex
50dcfe1637 gpu: nvgpu: update fb unit ecc init, handling
The ecc init, handling for the fb unit is refactored to improve reusability
for nvgpu-next.

The following changes have been done:
- fb.ecc:
  This is a new subunit within fb and contains the following functions:
  - init: Moved from fb.fb_ecc_init.
  - free: Moved from fb.fb_ecc_free.
  - l2tlb_error_mask: Fetch bit mask for corrected, uncorrected errors supported
    by the unit.
- fb.intr:
  This unit has been updated to include the following ecc interrupt, error
  handlers:
  - handle_ecc: Top level interrupt handler for fb ecc errors.
  - handle_ecc_l2tlb: Handle errors within l2tlb memory.
  - handle_ecc_hubtlb: Handle errors within hubtlb memory.
  - handle_ecc_fillunit: Handle errors within fillunit memory

Jira: NVGPU-5032

Change-Id: I1a26c1823eb992e0e0175250b969f1186dff6e62
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333271
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2020-12-15 14:13:28 -06:00
Seema Khowala
aff5497907 gpu: nvgpu: add intr_unit_bitmask i/p param for fb.intr.isr
tu104 onwards, fb interrupt status/enable/disable moved from
fb_niso_intr_* reg to fb_*vector* registers.
At the top level, fb interrupt status/enable/disable is done
using hub_intr bit in mc_intr registers.

Starting nvgpu-next, this has changed.

JIRA NVGPU-5032

Change-Id: Ib54170b055b83e2696312c811c2e3ba678749359
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2330867
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2020-12-15 14:13:28 -06:00
Sagar Kamble
a8c9c800cd gpu: nvgpu: reorganization of MC interrupts control
Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.

For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.

JIRA NVGPU-4336

Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
984fa5247a gpu: nvgpu: move replayable fault related code out of safety build
Moved mmu replayable fault related code under CONFIG_NVGPU_REPLAYABLE_FAULT
switch, so that it will be compiled out for safety build.

Following hals and their related code also moved under
CONFIG_NVGPU_REPLAYABLE_FAULT switch:
void (*handle_replayable_fault)(struct gk20a *g);
int (*mmu_invalidate_replay)(struct gk20a *g, u32 invalidate_replay_val);

JIRA NVGPU-4302

Change-Id: I191ee0c181b276a04bc1531488862380af81a5c9
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2227176
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2020-12-15 14:10:29 -06:00
Philip Elcan
51cf6317bb gpu: nvgpu: fb: reduce CCM for fb_int_ecc_gv11b
Reduce code complexity for gv11b_fb_intr_handle_ecc_fillunit(),
gv11b_fb_intr_handle_ecc_hubtlb() and gv11b_fb_intr_handle_ecc_l2_tlb(),
by creating helper functions for printing errors.

This reduces the TCC metric to 9 for all 3 functions.

JIRA NVGPU-4064

Change-Id: I13169352de6f4c6bf609be16861ecfa85bad0fa6
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2212889
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Sagar Kamble
ec293030c1 gpu: nvgpu: move non-safe functions from fusa hal to non-fusa hal
Multiple non-safe functions under NVGPU_DEBUGGER, NVGPU_CILP and other
config flags were moved to fusa files. Although they are guarded by
the C flags, it makes sense to keep those functions in non-fusa
files. Make this change for all hals.

JIRA NVGPU-3853

Change-Id: I8151b55a60cb50c5058af48bab9e8068f929ac3b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204352
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Rajesh Devaraj
935c5f6578 gpu: nvgpu: fix misra violations in SDL
This patch addresses misra violations due to SDL error reporting
callbacks. In particular, it addresses the following misra violation:

- misra_c_2012_directive_4_7_violation: Calling function
  "nvgpu_report_*_err()" which returns error information without testing
  the error information.

JIRA NVGPU-4025

Change-Id: Ia10b6b3fd9c127a8c5189c3b6ba316f243cedf04
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196895
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2020-12-15 14:05:52 -06:00
Adeel Raza
3107bc862b gpu: nvgpu: ifdef function prototypes in headers
ifdef function prototypes with CONFIG_* defines. This fixes MISRA rule
8.6 violations which complain about undefined functions.

JIRA NVGPU-3873

Change-Id: I4794eceed475672f347621ac25c09552a25d4ac1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195585
GVS: Gerrit_Virtual_Submit
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2020-12-15 14:05:52 -06:00
Philip Elcan
42f5a2d806 gpu: nvgpu: fb: fix CERT-C violations
CERT-C Rule INT30-C Requires that unsigned integer operations do not
wrap. Fix these violations by using the safe ops.

JIRA NVGPU-3868

Change-Id: I51e8ee212777232b6d7c033078bea9b9c77ff898
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166259
Reviewed-by: Automatic_Commit_Validation_User
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-08-05 16:56:33 -07:00
Rajesh Devaraj
fa6ada7619 gpu: nvgpu: disable hw error injection support in safety-release
This patch disables HW based fake error injection support in safety-release
build. For this purpose, it makes use of the following flag:
CONFIG_NVGPU_INJECT_HWERR.

JIRA NVGPU-3861

Change-Id: I1fa8544e67adbc53a1f3b98b340d76cf4f5bf524
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163289
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2019-07-30 04:09:31 -07:00
Sagar Kamble
7cae3709e0 gpu: nvgpu: split fb fusa/non-fusa hal
Moved gv11b_fb_intr_inject_hubmmu_ecc_error from fb_intr_ecc_gv11b.c to
fusa version and deleted that file. Moved debugger related functions
from fb_gm20b.c to fusa version. Updated arch yaml to reflect the fusa
and non-fusa fb units.

JIRA NVGPU-3690

Change-Id: I929169e9aac62e8377e4ea7e8353caa970999299
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156879
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-07-19 18:20:06 -07:00
Sagar Kamble
9bb347edec gpu: nvgpu: fix the hw header accessors
Various gv11b register accessors are passed as function pointer to
NVGPU_ECC_ERR. pmu logic needs access to head, tail, mutex registers
as function pointers. fix the same.

JIRA NVGPU-3733

Change-Id: I5668fedaac187fab052ee5d68a10f7e2d6d35413
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150880
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2019-07-12 06:20:44 -07:00
Debarshi Dutta
69ef86e627 gpu: nvgpu: move safe code HAL files to fusa
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.

Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.

Jira NVGPU-3690

Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-07-03 02:46:15 -07:00
Rajesh Devaraj
05ed37ae3a gpu: nvgpu: remove usage of hw headers from SDL
This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
    the initialization required for errors that can be injected using hw
    support, error injection function. Further, it passes the required
    information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
    nvgpu_report_ecc_err.

Jira NVGPU-3235

Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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2019-05-31 04:06:51 -07:00
Rajesh Devaraj
fcb7635a92 gpu: nvgpu: gops initialization for SDL
This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
  reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.

Jira NVGPU-3237

Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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2019-05-30 02:18:05 -07:00
Seema Khowala
dab5e445c9 gpu: nvgpu: add mmu_fault_tu104.[ch]
Move
mmu fault related functions from fb_tu104.c
to hal/fb/mmu_fault_tu104.c

Rename
mmfault to mmufault
fb_tu104_write_mmu_fault_buffer_lo_hi -> tu104_fb_write_mmu_fault_buffer_lo_hi
fb_tu104_read_mmu_fault_buffer_get -> tu104_fb_read_mmu_fault_buffer_get
fb_tu104_write_mmu_fault_buffer_get -> tu104_fb_write_mmu_fault_buffer_get
fb_tu104_read_mmu_fault_buffer_put -> tu104_fb_read_mmu_fault_buffer_put
fb_tu104_read_mmu_fault_buffer_size -> tu104_fb_read_mmu_fault_buffer_size
fb_tu104_write_mmu_fault_buffer_size -> tu104_fb_write_mmu_fault_buffer_size
fb_tu104_read_mmu_fault_addr_lo_hi -> tu104_fb_read_mmu_fault_addr_lo_hi
fb_tu104_read_mmu_fault_inst_lo_hi -> tu104_fb_read_mmu_fault_inst_lo_hi
fb_tu104_read_mmu_fault_info -> tu104_fb_read_mmu_fault_info
fb_tu104_read_mmu_fault_status -> tu104_fb_read_mmu_fault_status
fb_tu104_write_mmu_fault_status -> tu104_fb_write_mmu_fault_status
fb_tu104_mmu_invalidate_replay -> tu104_fb_mmu_invalidate_replay

JIRA NVGPU-1313

Change-Id: I01a8d3dfb9d2c7a92987076b7beabea8f3e9f0a5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107773
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2019-04-30 12:45:48 -07:00
Seema Khowala
1a85ecf1ed gpu: nvgpu: add include/nvgpu/mmu_fault.h
Move mmu_fault_info struct from mm.h to mmu_fault.h

Rename and move below hash defines to mmu_fault.h
NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY -> NVGPU_MMU_FAULT_NONREPLAY_INDX
NVGPU_MM_MMU_FAULT_TYPE_REPLAY -> NVGPU_MMU_FAULT_REPLAY_INDX
FAULT_TYPE_NUM -> NVGPU_MMU_FAULT_TYPE_NUM
NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX -> NVGPU_MMU_FAULT_NONREPLAY_REG_INDX
NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX -> NVGPU_MMU_FAULT_REPLAY_REG_INDX
NVGPU_FB_MMU_FAULT_BUF_DISABLED -> NVGPU_MMU_FAULT_BUF_DISABLED
NVGPU_FB_MMU_FAULT_BUF_ENABLED -> NVGPU_MMU_FAULT_BUF_ENABLED

JIRA NVGPU-1313

Change-Id: I3d4d56f881a5c3856c005db6dc7d850be4bc041d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107772
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2019-04-30 12:45:33 -07:00
Seema Khowala
906fd57c18 gpu: nvgpu: add fb/gmmu mmu_fault_gv11b.[ch]
Move mmu fault related functions from fb_gv11b.c
to hal/fb/fb_mmu_fault_gv11b.c and hal/mm/gmmu/gmmu_mmu_fault_gv11b.c

Rename
mmfault to mmufault
fb_gv11b_write_mmu_fault_buffer_lo_hi -> gv11b_fb_write_mmu_fault_buffer_lo_hi
fb_gv11b_read_mmu_fault_buffer_get -> gv11b_fb_read_mmu_fault_buffer_get
fb_gv11b_read_mmu_fault_buffer_put -> gv11b_fb_read_mmu_fault_buffer_put
fb_gv11b_read_mmu_fault_buffer_size -> gv11b_fb_read_mmu_fault_buffer_size
fb_gv11b_write_mmu_fault_buffer_size -> gv11b_fb_write_mmu_fault_buffer_size
fb_gv11b_read_mmu_fault_addr_lo_hi -> gv11b_fb_read_mmu_fault_addr_lo_hi
fb_gv11b_read_mmu_fault_inst_lo_hi -> gv11b_fb_read_mmu_fault_inst_lo_hi
fb_gv11b_read_mmu_fault_info -> gv11b_fb_read_mmu_fault_info
fb_gv11b_read_mmu_fault_status -> gv11b_fb_read_mmu_fault_status
fb_gv11b_write_mmu_fault_status -> gv11b_fb_write_mmu_fault_status
gv11b_fb_parse_mmfault -> gv11b_fb_parse_mmu_fault_info
gv11b_fb_print_fault_info -> gv11b_fb_mmu_fault_info_dump

Rename and move to gmmu
gv11b_fb_parse_mmu_fault_info -> gv11b_gmmu_parse_mmu_fault_info
gv11b_fb_handle_mmu_nonreplay_replay_fault -> gv11b_gmmu_handle_mmu_nonreplay_replay_fault
gv11b_fb_handle_mmu_fault_common -> gv11b_gmmu_handle_mmu_fault_common
gv11b_fb_handle_other_fault_notify -> gv11b_gmmu_handle_other_fault_notify

JIRA NVGPU-1313

Change-Id: Ia69a0b6b50347d11764e3ff34a5ea67ea8d64915
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107771
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-30 12:45:19 -07:00
Seema Khowala
66cb9495a5 gpu: nvgpu: move mmu_fault_pending ops out from mm
Moved
-mmu_fault_pending mm ops to is_mmu_fault_pending mc ops
-mmu_fault_pending fb ops to is_mmu_fault_pending fb.intr ops. This
is needed to check if mmu fault intr is pending for volta onwards.

Added
is_mmu_fault_pending fifo ops. This is needed to check if mmu fault
interrupt is pending for chips prior to volta

JIRA NVGPU-1313

Change-Id: Ie8e778387cd486cb19b18c4aee734c581dcd9229
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094895
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-11 22:25:01 -07:00
Seshendra Gadagottu
9c465d5fd5 gpu: nvgpu: move fb interrupt handling to fb intr sub-unit
Moved fb interrupt handling related code to fb intr sub-unit.

Moved following hals from fb hal to fb intr hal and renamed to:
void (*enable)(struct gk20a *g);
void (*disable)(struct gk20a *g);
void (*isr)(struct gk20a *g);

gk20a_readl/writel are replaced with nvgpu_read/writel.
Hals are populated with new function names and code is modified
to call new hals.

Moved ecc interrupt to gv11b_fb_intr_handle_ecc in a separate file:
fb_intr_ecc_gv11b.c/h

JIRA NVGPU-2034

Change-Id: I80c7110c902c4e082561cf7cbe65c20eb9acb661
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-09 15:35:16 -07:00