Commit Graph

7 Commits

Author SHA1 Message Date
Sagar Kamble
b6b56bd556 gpu: nvgpu: isolate common & hal falcon_reset functions
nvgpu_falcon_reset should handle engine specific falcon reset or resort to
falcon CPU reset. gk20a_falcon_reset is supposed to be hal API that will
reset the falcon CPU. Hence move the dependent engine reset to
nvgpu_falcon_reset.

JIRA NVGPU-1459

Change-Id: I1b15f31a8bbb515736af5b0122ce206be0811bbc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015590
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-14 02:27:54 -08:00
Sagar Kamble
c2a1cc5ff8 gpu: nvgpu: remove unneeded falcon struct members
Remove unneeded members from falcon struct - flcn_core_rev, isr_enabled,
isr_mutex, intr_mask & intr_dest.

JIRA NVGPU-1459

Change-Id: I682666355778c1ac9ff0ffae014ff3271f9149a7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015587
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-14 02:27:39 -08:00
Mahantesh Kumbar
a759ee0ec8 gpu: nvgpu: get PMU ucode cmd line args DMEM offset
Fetch DMEM size of PMU falcon using common Falcon
interface to copy PMU ucode command lines args
at top of PMU DMEM offset.

Change needed to cleanup dependency between PMU and ACR

JIRA NVGPU-1147

Change-Id: Ie0b1bcf0bdd1afb2c37c1a7d061dc9b03f9fc679
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012082
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-11 03:28:37 -08:00
Mahantesh Kumbar
4e59575af2 gpu: nvgpu: FBQ falcon queue functions
-FBQ(command/message queue) will be part of super surface
 which will reside in FB.
-FBQ access should happen using falcon generic queue functions
 so added FBQ related functions under flacon queue as needed
 to support FBQ.
-Additional FBQ related public functions exposed as command buffer is
 constructed in sysmem buffer which will be copied to actual FBQ element
 buffer & also, payload is part of queue element which needs some queue
 parameters access from client

JIRA NVGPU-1577
Bug 2487534

Change-Id: I1b9d9d999e73af3dabe54240c16676ff8d0c21fa
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2004019
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-30 22:35:10 -08:00
Konsta Holtta
0aeb2a6f87 Revert "gpu: nvgpu: FBQ falcon queue functions"
This reverts commit cfca282e32.

Bug 2487534

Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Change-Id: If8259293c6d1d554155b100eaf435587a6eab5b7
Reviewed-on: https://git-master.nvidia.com/r/2001921
2019-01-23 08:26:02 -08:00
Mahantesh Kumbar
cfca282e32 gpu: nvgpu: FBQ falcon queue functions
-FBQ(command/message queue) will be part of super surface
 which will reside in FB.
-FBQ access should happen using falcon generic queue functions
 so added FBQ related functions under falcon queue as needed
 to support FBQ.
-Additional FBQ related public functions exposed as command
 buffer is constructed in sysmem buffer which will be copied
 to actual FBQ element buffer & also, payload is part of queue
 element which needs some queue parameters access from client

JIRA NVGPU-1577

Change-Id: I3ae097e378fd162bb779aaae986b2fae306238d9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1777939
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-20 23:16:11 -08:00
Sagar Kamble
48c0a239e7 gpu: nvgpu: create falcon private header
Add common/falcon/falcon_priv.h file that will contain declarations
private to Falcon unit. Clean up the falcon header files inclusion.
Rules followed:
1. Remove unneeded header file includes.
2. Falcon unit source files will only include falcon_priv.h.
3. Base architecture Falcon source (falcon_gk20a.c) will only
   include hw_falcon_*.h file.
4. Derived architecture source will include hw headers if needed.
5. Other units should not include hw headers for Falcon.
6. HAL source will include the Falcon unit header if needed.

JIRA NVGPU-1459

Change-Id: Ia9f03f7b577fe10b8c0f417e6302fa7ebd4131cc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1961634
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-03 02:58:51 -08:00