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gpu: nvgpu: remove unneeded falcon struct members

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Remove unneeded members from falcon struct - flcn_core_rev, isr_enabled,
isr_mutex, intr_mask & intr_dest.

JIRA NVGPU-1459

Change-Id: I682666355778c1ac9ff0ffae014ff3271f9149a7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015587
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-02-06 11:59:39 +05:30
committed by mobile promotions
parent ddcdf364b7
commit c2a1cc5ff8
3 changed files with 7 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -143,9 +143,7 @@ void nvgpu_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
flcn_ops = &flcn->flcn_ops;
if (flcn_ops->set_irq != NULL) {
flcn->intr_mask = intr_mask;
flcn->intr_dest = intr_dest;
flcn_ops->set_irq(flcn, enable);
flcn_ops->set_irq(flcn, enable, intr_mask, intr_dest);
} else {
nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ",
flcn->flcn_id);

7
drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c
View File

@@ -70,7 +70,8 @@ static bool gk20a_falcon_clear_halt_interrupt_status(struct nvgpu_falcon *flcn)
return status;
}
static void gk20a_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable)
static void gk20a_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
u32 intr_mask, u32 intr_dest)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
@@ -84,9 +85,9 @@ static void gk20a_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable)
if (enable) {
gk20a_writel(g, base_addr + falcon_falcon_irqmset_r(),
flcn->intr_mask);
intr_mask);
gk20a_writel(g, base_addr + falcon_falcon_irqdest_r(),
flcn->intr_dest);
intr_dest);
} else {
gk20a_writel(g, base_addr + falcon_falcon_irqmclr_r(),
0xffffffffU);

8
drivers/gpu/nvgpu/common/falcon/falcon_priv.h
View File

@@ -174,7 +174,8 @@ struct nvgpu_falcon_engine_dependency_ops {
struct nvgpu_falcon_ops {
int (*reset)(struct nvgpu_falcon *flcn);
void (*set_irq)(struct nvgpu_falcon *flcn, bool enable);
void (*set_irq)(struct nvgpu_falcon *flcn, bool enable,
u32 intr_mask, u32 intr_dest);
bool (*clear_halt_interrupt_status)(struct nvgpu_falcon *flcn);
bool (*is_falcon_cpu_halted)(struct nvgpu_falcon *flcn);
bool (*is_falcon_idle)(struct nvgpu_falcon *flcn);
@@ -204,13 +205,8 @@ struct nvgpu_falcon {
struct gk20a *g;
u32 flcn_id;
u32 flcn_base;
u32 flcn_core_rev;
bool is_falcon_supported;
bool is_interrupt_enabled;
u32 intr_mask;
u32 intr_dest;
bool isr_enabled;
struct nvgpu_mutex isr_mutex;
struct nvgpu_mutex copy_lock;
struct nvgpu_falcon_ops flcn_ops;
struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops;