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499 Commits

Author SHA1 Message Date
Thomas Fleury
569b781cb2 gpu: nvgpu: unit: skip falcon dump for fifo intr 
Register address space for falcon is not registered
and g->ops.gr.falcon.dump_stats is triggering multiple
ABORTs while testing gv11b_fifo_intr_0_isr.

Use stub for g->ops.gr.falcon.dump_stats.

Jira NVGPU-4386

Change-Id: I6fb2b9b59f533626fce49bf4d3ff72cb8a1a6c44
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264850
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Prateek sethi
28d21878a7 gpu: nvgpu: fix memory fault in invalid_pd_alloc 
nvgpu_pd_alloc() calls gk20a_from_vm which is extracting g from
vm->mm->g without assigning mm pointer to vm->mm. Assigning the
pointers.

Bug 200577095

Change-Id: Ibe2757b0616fd8e87df509abe5d85e90d989d45c
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264751
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
ae8f71a462 gpu: nvgpu: unit: add therm unit test 
Add unit test for common.therm and gv11b therm HALs.

JIRA NVGPU-936

Change-Id: Iff857ad24eac729b5f7bf9868c1f05becefbaaad
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260441
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 2020-12-15 14:10:29 -06:00
vinodg
3400d1b6be gpu: nvgpu: branch coverage for gr.falcon hal 
Update gr.falcon hal test for branch coverage.
Generate expected bug by passing 64bit value for falcon.bind_instblk.

Jira NVGPU-4453

Change-Id: I735f96f21e54fce199a47c37043acc81006ee806
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264321
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
2f9548c1f8 gpu: nvgpu: Add test cases for ACR construct execute code 
Adding more test cases to cover fail/negative scenarios
and more branches in the nvgpu_acr_construct_execute() code

JIRA NVGPU-4319

Change-Id: I998f914abf9ba592a3a014698efaa2437236f448
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263868
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
61315f0fbb gpu: nvgpu: Add test cases for HS bootstrap code 
Adding more test cases to cover fail/negative scenarios
and more branches in the nvgpu_acr_bootstrap_hs_acr() code

JIRA NVGPU-4319

Change-Id: Ib8b154f7e59e60971bb231cf7dbe0b9b3f209384
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263203
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 2020-12-15 14:10:29 -06:00
ddutta
83103cdcca gpu: nvgpu: move set_min_max out of safety build 
nvgpu_channel_sync_set_min_eq_max is not used as part of the safety
build and hence is moved out. channel_sync_syncpt_set_min_eq_max is
also moved out as a part of the above function.

Also add a branch coverage for the case when g->disable_syncpoints is
set to true.

Jira NVGPU-913

Change-Id: I2512d01e105551732aad63b2800bb4cb6d913cb2
Signed-off-by: ddutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263003
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 2020-12-15 14:10:29 -06:00
Antony Clince Alex
81720e81fa nvgpu: userspace: update tests to use mock-iospace library 
Remove mocked IO space definitions from units like fifo and gr, instead
get these from mock-iospace library.

Jira: NVGPU-4520

Change-Id: I397e0bccdb4f744d9dd7fb57d2a2a504abcc618b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261826
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
9a89b94a68 gpu: nvgpu: falcon: fix test_falcon_bootstrap 
After hs_ucode_bootstrap the PMU falcon registers were being checked
incorrectly. Fix the logic and update the register offsets with that
of GPCCS registers.

JIRA NVGPU-2214

Change-Id: Ic28cd8eb6894fc16418434a95e46f81095861892
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261166
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 2020-12-15 14:10:29 -06:00
Antony Clince Alex
8ffbd7faff nvgpu: userspace: bundle mocked IO space definitions into library 
At present each nvgpu test unit defines its own mocked IO space. This is used to
intialize the qnx/posix IO framework. This results in unwanted redefinitions,
bloating of the binary. This patch creates a shared library which contains all
the mocked IO space definitions and it exports a function which enable units to
query, get access to the mocked IO space.

Jira: NVGPU-4520

Change-Id: Ied19f14e25274953e15a785b3a73053d84012b80
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260042
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
b1e4c0ef72 gpu: nvgpu: falcon: add unit tests for branch coverage 
Add test case to cover gk20a_is_falcon_idle branches, non-word multiple
copy cases in copy to imem and dmem, buffering logic in unaligned data
copy to imem/dmem.

Also update falcon_copy_to_dmem|imem_unaligned_src logic to compare the
offset with size.

JIRA NVGPU-2214

Change-Id: Ib891dc57f36a66818837f951c4453588b71fed90
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259146
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
70f614e07e gpu: nvgpu: falcon: add boundary value test for copy to memory 
Copy to falcon's IMEM and DMEM begins at offset that lies between 0 and
(IMEM/DMEM size - 1). Hence update the validation check. Add the test
case with offset set to the size of IMEM/DMEM that covers all branches
in the function falcon_memcpy_params_check.

JIRA NVGPU-2214

Change-Id: I4807331302014a1b012aa6c05919865b49c86dec
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258312
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
6eef1a486c gpu: nvgpu: falcon: add unit tests and update functions 
Add unit tests to cover the invalid falcon port access, falcon sw init
switch cases, nvgpu_falcon_set_irq, nvgpu_timeout_init failure branch
coverage.

Compile out the functions nvgpu_falcon_get_mem_size & falcon_bootstrap
as they are needed by LS PMU and VBIOS code. For iGPU safety the
falcon functions needing these will call the HAL APIs directly.
This way we avoid the unreachable code as well. Updated the
prototype of falcon bootstrap HAL API as that doesn't return
any error.

With these changes, we get 100% line coverage for common.falcon unit.

JIRA NVGPU-2214

Change-Id: I1fe653d97c1a6a1521d7da38f171928dda58c5b5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258311
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
fba516ffae gpu: nvgpu: enable PMU ECC interrupt early 
PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.

Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.

PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.

Update the doxygen for changed functions.

JIRA NVGPU-4439

Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2251732
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
359fc35fa8 gpu: nvgpu: unit: fifo: runlist unit test 
This unit test covers most of the nvgpu.common.fifo.runlist module lines
and almost all branches.

Jira NVGPU-3699
Jira NVGPU-4135

Change-Id: Ie15579a3c5f7903c2e25ba973078636edea712c9
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2227154
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 2020-12-15 14:10:29 -06:00
Nicolas Benech
533d9e1dc0 gpu: nvgpu: unit: fix crash in handle_bar2_fault test 
In release config, the handle_bar2_fault test was failing. This
was caused by pointers to string not being initialized in the
mmu_fault_info structure.

JIRA NVGPU-932

Change-Id: Ie47f414c3701b851dc175bed19b68d9c9aec87d9
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264181
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
cb117411ca gpu: nvgpu: cg: update the gating reglist hals 
pwr_csb slcg, blcg gating registers are covered by pmu slcg/blcg hence
its load functions are not used. Hence, delete the generated data and
functions. slcg, blcg ctxsw_firmware and pg_gr gating reglists are
null hence delete the generated data and functions.

JIRA NVGPU-2175

Change-Id: Ib04d9845331c9a287666d3b8c974e1d3b66a7677
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263272
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
4eca7b806c gpu: nvgpu: cg: load therm unit SLCG gating registers 
Therm unit SLCG hal was not called earlier. Call it from
nvgpu_init_therm_support and add unit tests.

JIRA NVGPU-2175

Change-Id: I158878f4a49e580c7addeff619e0a838020c7987
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263271
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
fdb8046812 gpu: nvgpu: unit: add negative tests for common.gr.obj_ctx 
Add negative tests that inject memory allocation failures and
HAL function call errors to verify error handling path in
common.gr.obj_ctx unit.

Update common.gr.setup test to cover invalid class input while
setting preemption mode.

Jira NVGPU-4457

Change-Id: I74d1ba63ba8aace6087b51fd50e2c136822d3a00
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260939
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
71040ef04f gpu: nvgpu: unit: mm: mmu_fault gv11b_fusa UT 
This unit test covers most of the nvgpu.hal.mm.mmu_fault.gv11b_fusa
module lines and almost all branches.

Jira NVGPU-2218

Change-Id: I7c95876a0b1b4bb4b86eb15e21ca0da747d06162
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258545
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 2020-12-15 14:10:29 -06:00
tkudav
8e37e590b4 gpu: nvgpu: unit: unit tests for common.bus 
Add unit tests for common.bus unit.

JIRA NVGPU-928

Change-Id: I0ac146e270890ea703b1a45add7f36c1b08451a5
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258297
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
c404af5575 gpu: nvgpu: unit: mm: hal/gmmu/ unit tests 
This unit test covers most of the nvgpu.hal.gmmu module lines and
almost all branches.

Jira NVGPU-2218

Change-Id: Ibf73a090ec1195b7dc1c8827967f0e7c773228da
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254733
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
f31171a667 gpu: nvgpu: unit: mm: flush_gv11b_fusa unit test 
This unit test covers most of the nvgpu.hal.mm.cache.flush_gv11b_fusa
module lines and almost all branches.

Jira NVGPU-2218

Change-Id: I565cf289079f754d3f76b6680e853d1859c52283
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248383
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
1fa65bcc13 gpu: nvgpu: unit: mm: gp10b_fusa unit test 
This unit test covers most of the nvgpu.hal.mm.gp10b_fusa module lines
and almost all branches.

Jira NVGPU-2218

Change-Id: I16be22aefd10b8a8ee456f33619ecaf28776a072
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248083
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
80e9a7428a gpu: nvgpu: unit: mm: gv11b_fusa unit test 
This unit test covers most of the nvgpu.hal.mm.gv11b_fusa module lines
and almost all branches.

Jira NVGPU-2218

Change-Id: I5f0e766329321d29ef1d22ce1e07264562ca124a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248082
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
a73ca0b70e gpu: nvgpu: split GR ECC initialization 
Split GR ECC initialization into GPC/TPC and FECS ECC init as FECS ECC
errors during acr_construct_execute need to be reported and handled
hence FECS ECC counters are required to be initialized before
acr_construct_execute.

GPC/TPC ECC counters are dependent on the GR config that will be
initialized only after acr_construct_execute.

nvgpu_gr_intr_init_support is moved to nvgpu_gr_prepare_sw.

FECS ECC interrupt is enabled by default hence interrupt is not
enabled through gr_fecs_host_int_enable_r in nvgpu_gr_prepare_sw.

JIRA NVGPU-4439

Change-Id: Ifc9912f0578015a6ba1e9d38765c42633632b15f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261987
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
2fe78b4a31 gpu: nvgpu: unit: improve branch coverage for pbdma 
Improve branch coverage for:
- nvgpu_pbdma_find_for_runlist

Jira NVGPU-3490

Change-Id: I28a0b86f92a6912cb4046145c0fcc9ec9efc360f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263620
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:10:29 -06:00
Nicolas Benech
92d5c53c59 gpu: nvgpu: unit: add fb HAL unit tests 
Unit tests covering the FB related HALs.

JIRA NVGPU-932

Change-Id: I46de25ea2a495e22ca6485d1fae1778261a804bd
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259666
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
0285ca6d98 gpu: nvgpu: unit: fifo: preempt unit test 
This unit test covers most of the nvgpu.common.fifo.preempt module lines
and almost all branches.

Jira NVGPU-3698

Change-Id: I3960cd77c88126659e4d990f4d27dc43850f9ae4
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2236730
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 2020-12-15 14:10:29 -06:00
vinodg
c25ccbb130 gpu: nvgpu: Add negative test for gr.config unit 
Add test to coverage the error injections in gr.config unit.
required_tests is updated with new test for gr.config and
missing test for gr.setup unit.

Jira NVGPU-4531

Change-Id: Idf089af5fec1e653793a620b4e7f7bd5d96210ba
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262230
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
0ede89f859 gpu: nvgpu: Tests for gr.intr unit branch coverage. 
More test added for gr.intr units common and hal codes.
Update doxygen for gr.unit test.

Jira NVGPU-4454

Change-Id: Ifcebb437bff22fb6b6522763d2bb8e5c58bdfdd7
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260887
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
5f0d1f39c2 gpu: nvgpu: unit: create mc unit test 
JIRA NVGPU-2224

Change-Id: Ic433e8bc2ac583c1735203d1b5f0fd61942c33d4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2257128
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
dcd1e423b4 gpu: nvgpu: unit: cond: use nvgpu_thread's 
The cond unit test was using native pthreads for threads. This change
updates the posix-cond unit test to use the nvgpu_threads interface to
create threads. This ensures the fault injection is setup correctly in
the threads used in the test.

JIRA NVGPU-2224

Change-Id: I94067d25d109cf0569e0c9d83825fefbfc36701a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258704
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
ddutta
c282005e42 gpu: nvgpu: add UT coverage for nvgpu_channel_sync_syncpt 
Add coverage for the following APIs in the common.sync.syncpt unit.
nvgpu_channel_sync_to_syncpt
nvgpu_channel_sync_get_syncpt_id
nvgpu_channel_sync_get_syncpt_address

In the test "test_sync_create_fail" the branch syncpt_ro_map_gpu_va_fail
wasn't working correctly. This patch adds a change that makes it
execute correctly.

Jira NVGPU-913

Change-Id: I5551e49ebd9567d0b4866fada494eec300893f6a
Signed-off-by: ddutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259898
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
2ccfb46072 gpu: nvgpu: power_features: add unit tests for more coverage 
Add test cases for verifying disabling the prod gating and test cases
for covering remaining branches and lines.

JIRA NVGPU-2175

Change-Id: Iaa6d4cade35d80f26710b8a994e874c26c52b3fa
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260172
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
e721335dd6 gpu: nvgpu: Covering more branches in ACR 
Adding more test cases
- to cover fail scenario for
  nvgpu_falcon_wait_for_halt()
- to cover memory allocation failure in the function
  nvgpu_acr_bootstrap_hs_acr() and nvgpu_acr_lsf_fecs_ucode_details()

JIRA NVGPU-4319
Change-Id: I171a2bf682ed16ae6c025d24f0238b159d67746b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259940
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
38bcba3190 gpu: nvgpu: unit: add coverage for tsg 
Add/improve coverage for the following functions:
- nvgpu_tsg_open
- nvgpu_tsg_release
- nvgpu_tsg_bind
- nvgpu_tsg_unbind
- nvgpu_tsg_mark_error
- nvgpu_tsg_set_ctx_mmu_error
- nvgpu_tsg_reset_faulted_eng_pbdma

Update list of required tests in JSON file.

Jira NVGPU-4387

Change-Id: Ic389c91d8cf98ba5dca312a4a3a96e0c6d1c6b97
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248161
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
1fc9a427e0 gpu: nvgpu: tear down TSG on unbind HAL failure 
Currently nvgpu_tsg_unbind ignores return code from
g->ops.tsg.unbind_channel. For consistency, tear down
TSG in case an error occurs in the unbind HAL.

Also make sure to restore valid ops for fifo.preempt_tsg
in test_gr_setup_free_obj_ctx, to avoid unbind failure.

Jira NVGPU-4387

Change-Id: I27a9c0daa365d05684149fc4bb17874d60ae1fde
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248159
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Debarshi Dutta
25adc8d587 gpu: nvgpu: add UT coverage for sync unit 
This patch adds full branch coverage for the functions
nvgpu_channel_sync_create and nvgpu_channel_sync_destroy.

Jira NVGPU-913

Change-Id: Iab9922ccd57873f0aab452805ea506b4b2601d5d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254954
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
80f408632a gpu: nvgpu: unit: add negative tests for common.gr.ctx 
Add negative tests that inject memory allocation failures and verify
error handling path in common.gr.ctx unit.

Update common.gr.global_ctx unit test to check if global context
buffers are ready after allocation call.

Jira NVGPU-4373

Change-Id: Ia373441819257890f9f10667e6e2e363081a6757
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259074
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
f0f6c77c01 gpu: nvgpu: Add tests for code coverage in gr.falcon 
Add more tests for branch and line coverages in gr.falcon
common and hal code.

Jira NVGPU-4453

Change-Id: Ie01bac73ad18773bba1c27bf4bcb2b2776970f29
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258557
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
83ef099d19 gpu: nvgpu: unit: add negative tests for common.gr.global_ctx 
Add negative tests that inject memory allocation failures and verify
error handling path in common.gr.global_ctx unit.

Jira NVGPU-4373

Change-Id: Ic180f5eda0d25d5a713bdd513a617dc7c3a29d53
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255770
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
4f45ec7d5f gpu: nvgpu: unit: mm: flush_gk20a_fusa unit test 
This unit test covers most of the nvgpu.hal.mm.cache.flush_gk20a_fusa
module lines and almost all branches.

Jira NVGPU-2218

Change-Id: I1c090a301a7d1fddb675248287e7d4c7b9da0538
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248084
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
23bbce1102 gpu: nvgpu: unit: add tests for gv11b fifo HAL 
Add unit tests for the following HALs:
- gv11b_init_fifo_reset_enable_hw
- gv11b_init_fifo_setup_hw
- gv11b_fifo_mmu_fault_id_to_pbdma_id
- gv11b_fifo_intr_0_enable
- gv11b_fifo_handle_sched_error
- gv11b_fifo_intr_0_isr
- gv11b_fifo_intr_set_recover_mask
- gv11b_fifo_intr_unset_recover_mask

Jira NVGPU-4386

Change-Id: I888aca62e8eb8223a1def693a5ed51500baa37fc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256265
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
4c43d83032 gpu: nvgpu: unit: add tests for gk20a fifo HAL 
Add unit tests for the following HALs:
- gk20a_fifo_init_pbdma_map
- gk20a_fifo_get_runlist_timeslice
- gk20a_fifo_get_pb_timeslice
- gk20a_fifo_intr_1_enable
- gk20a_fifo_intr_1_isr
- gk20a_fifo_intr_handle_chsw_error
- gk20a_fifo_intr_handle_runlist_event
- gk20a_fifo_pbdma_isr

Jira NVGPU-4386

Change-Id: Iab518e3bc3f8fabdfb32172db8de300dd4142a53
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256264
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
5a17ccb83f gpu: nvgpu: unit: test coverage for gr.ecc unit 
Add more test for line/branch coverages in gr.ecc
common and fusa code.
Max gpc_count is one for gv11b, add a checking under
CONFIG_NVGPU_NON_FUSA to avoid unwanted error handling.

Jira NVGPU-4460

Change-Id: Ifac53394ebe58698b81e1e108731ccc36d624ff3
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256451
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
76adb91f60 gpu: nvgpu: unit: add CE unit test 
Add unit test for the common.ce unit and the gv11b CE FUSA HALs.

JIRA NVGPU-930

Change-Id: Idee75a1a5b53d397047edbead0db68ae999ce640
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255473
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
42feb5e21f gpu: nvgpu: unit: update valid classes for safety 
VOLTA_A class is not a valid class for safety. So moved
this class from valid class list to invlaid class list.

JIRA NVGPU-4314

Change-Id: Iea2f655628aaf31f9067a705919869174facfc91
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255325
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Tested-by: Sami Kiminki <skiminki@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
3d202fcceb gpu: nvgpu: unit: ltc: add test for flush_ltc HAL 
Add test for gm20b_flush_ltc HAL.

JIRA NVGPU-2219

Change-Id: Idf1e658ac06207b74dbec0ebd2234adc458282be
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255350
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
feeb978c91 gpu: nvgpu: unit: define required pbdma HAL tests 
Update JSON file with list of required pbdma HAL tests.

Jira NVGPU-3694

Change-Id: I9b6487a124ebac5de8d7d04999dcf76b4163a61d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254417
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00