rmylavarapu
8e545ef04b
gpu: nvgpu: Fix boardobj allocation size
...
In current implementation we are allocating boardobj
in nvgpu_boardobj_construct_super for all units and assigning
that pointer to boardobj type, as the size differe for different
units assigning the boardobj pointer to a common type will
give violations. Fixing them by allocating mem a head
and later call construct_super for elements initialization.
NVGPU-4484
Change-Id: I9b5ed1a6d8418fec48a29eee38d55fc7d83fcfab
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335989
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2020-12-15 14:13:28 -06:00
rmylavarapu
0115c26f1b
gpu: nvgpu: Boardobj lite unit refactor
...
As boardobj unit is used only in PMU, the plan is to move
all the boardobj related functions/structures and Macros
to boardobj specific folders. This will remove unnecessary
usage of boardobj outside PMU.
NVGPU-4484
Change-Id: I9f0fda32e6affd1fce218eb0ac638a9dfc8b99c3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com >
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2020-12-15 14:13:28 -06:00
Alex Waterman
5f0fdf085c
nvgpu: unit: Add new mock register framework
...
Many tests used various incarnations of the mock register framework.
This was based on a dump of gv11b registers. Tests that greatly
benefitted from having generally sane register values all rely
heavily on this framework.
However, every test essentially did their own thing. This was not
efficient and has caused a some issues in cleaning up the device and
host code.
Therefore introduce a much leaner and simplified register framework.
All unit tests now automatically get a good subset of the gv11b
registers auto-populated. As part of this also populate the HAL with
a nvgpu_detect_chip() call. Many tests can now _probably_ have all
their HAL init (except dummy HAL stuff) deleted. But this does
require a few fixups here and there to set HALs to NULL where tests
expect HALs to be NULL by default.
Where necessary HALs are cleared with a memset to prevent unwanted
code from executing.
Overall, this imposes a far smaller burden on tests to initialize
their environments.
Something to consider for the future, though, is how to handle
supporting multiple chips in the unit test world.
JIRA NVGPU-5422
Change-Id: Icf1a63f728e9c5671ee0fdb726c235ffbd2843e2
Signed-off-by: Alex Waterman <alexw@nvidia.com >
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
b8f398f6a7
gpu: nvgpu: clean up struct priv_cmd_entry
...
The valid flag is no longer useful as the lifetime of priv cmd entries
is clearer than before. Delete it. Delete also the stored gva that can
be calculated from the nvgpu_mem plus offset.
Jira NVGPU-4548
Change-Id: Ibf322acbb2ab1a454e9b644af24c02d291b75633
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
(cherry picked partially from commit
b9f6512e803873aaa92218dcbc090ff31a4f9c50)
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2020-12-15 14:13:28 -06:00
Seema Khowala
d03883d09d
gpu: nvgpu: do not use nvgpu_writel_check in gm20b_flush_ltc
...
Replace nvgpu_wriel_check with nvgpu_writel to issue clean
and invalidate in gm20b_flush_ltc.
JIRA NVGPU-5490
Change-Id: I6e1e73136e93ff06396894e5ba855f30bc3403b0
Signed-off-by: Seema Khowala <seemaj@nvidia.com >
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
ee216bc941
gpu: nvgpu: add NVGPU_SUPPORT_COMPRESSION flag
...
Add NVGPU_SUPPORT_COMPRESSION to indicate if compression feature is
supported in nvgpu. If not, set cbc.init, cbc.ctrl and
cbc.alloc_comptags hals to NULL.
Add corresponding GPU characteristics flag and IOCTL mapping to sync
compression support status with nvrm_gpu.
JIRA NVGPU-4666
Change-Id: I2e685688ddac592b3bb918ee70c82ea5524d695a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
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2020-12-15 14:13:28 -06:00
Seema Khowala
cfc5bac059
gpu: nvgpu: add assert in nvgpu_writel_check
...
nvgpu_writel_check outputs dbg message if updated read value
does not match with requested write value. Change dbg message to
error message.
Use BUG_ON for write mismatch as failure to update h/w register
is a bug and tells s/w to either add fixed delay or use timeout
to check for updated register value.
JIRA NVGPU-5490
Change-Id: Ib11b7862d2990a56259d2f8c10d75c12c84bae5d
Signed-off-by: Seema Khowala <seemaj@nvidia.com >
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
e5b23f33b9
gpu: nvgpu: add internal CONFIG_SYNC wrapper
...
The sync file support in Linux has been stabilized and the new config is
called CONFIG_SYNC_FILE. Even if maybe not so intended, both the
stabilized version and the legacy CONFIG_SYNC can coexist; to begin with
supporting the stabilized version, add CONFIG_NVGPU_SYNCFD_ANDROID and
CONFIG_NVGPU_SYNCFD_NONE as choice configs of which one will be set. A
later patch will extend this with a choice for CONFIG_SYNC_FILE.
Jira NVGPU-5353
Change-Id: I67582b68d700b16c46e1cd090f1b938067a364e3
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336118
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
068e00749b
gpu: nvgpu: update config_userd_writeback_enable
...
Field value of pbdma_config_userd_writeback_enable is changing from
0x1 to 0x0 for nvgpu-next. So,
- Update config_userd_writeback_enable() hal to accept u32 value.
- Update config_userd_writeback_enable() hal to return modified
value after setting pbdma_config_userd_writeback_enable field.
Jira NVGPU-5162
Change-Id: I94efa20c34bb867f185778c973bd52b86902b32c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
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2020-12-15 14:13:28 -06:00
Nicolas Benech
4267008096
gpu: nvgpu: debug: remove unused dentry pointers
...
Starting with kernel 5.7-rc3, the debugfs_create_u32 function returns
void instead of (struct dentry *). The rationale was that the
returned value was never used, and indeed it was not used within
NVGPU.
JIRA HK123-39
Change-Id: Ic8c2aaf9c84bcf016ed7a0183d84da311e4027d0
Signed-off-by: Nicolas Benech <nbenech@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2337859
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
cd7194cbc0
gpu: nvgpu: modify gmmu page table entry functions
...
Move below chip agnostic gmmu pte functions to common/mm/gmmu/pte.c.
- gmmu_aperture_mask()
- pte_dbg_print()
Default big page size for all chips is 64K. So, move
gp10b_mm_get_default_big_page_size() to common file and rename as
nvgpu_gmmu_default_big_page_size().
Modify gv11b_gpu_phys_addr() to use get_iommu_bit() hal.
JIRA NVGPU-4666
Change-Id: I512c42723faf2d03e5b367879c9c385dcf52cdc2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
05df07945a
gpu: nvgpu: avoid channel dependency in priv cmdbuf
...
The priv cmdbuf queue needs only the vm_gk20a of the channel that owns
it. Pass the vm to the queue constructor and have the channel code store
the queue to itself instead of poking at the channel from the queue
code. Adjust the cmdbuf queue api to take the queue, not the channel.
Move the inflight job fallback calculation to the channel code. The size
of the channel gpfifo isn't needed in the queue; just the job count is.
[not part of the cherry-pick: a bunch of MISRA mitigations.]
Jira NVGPU-4548
Change-Id: I4277dc67bb50380cb157f3aa3c5d57b162a8f0ba
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329659
(cherry picked from commit 83b2276f7bea563602eee20ce24b70ce70c8475a)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
991002c88b
gpu: nvgpu: hide struct priv_cmd_entry
...
The type for entries allocated from the priv cmd queue is no longer
necessary to be visible for its users other than as an opaque handle,
except for a few minor debug prints. Make those prints output the entry
pointer value instead and move the struct definition to priv_cmdbuf.c.
Jira NVGPU-4548
Change-Id: Ia75ff41d840ac928561525a46d5973640e4b5f7e
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329658
(cherry picked from commit 3292cdadbc78ca129d1e0878c3947b0839487fc2)
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2020-12-15 14:13:28 -06:00
Antony Clince Alex
b436877190
gpu: nvgpu: replace nvgpu_log with nvgpu_err for CE stall interrupts
...
Replace nvgpu_log with nvgpu_err for ce stall interrupt messages.
Jira: NVGPU-5034
Change-Id: I794461431ec6fadc322fe05a4f53f619c5370052
Signed-off-by: Antony Clince Alex <aalex@nvidia.com >
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2020-12-15 14:13:28 -06:00
Abdul Salam
076c85f813
gpu: nvgpu: Move clk_pmu struct from public include to unit include
...
As a part of refactoring move nvgpu_clk_pmupstate from public to
private include.
Also remove all function pointers from the struct and use functions
as only single pstate is supported.
This function pointers were created to address multiple pstate support
which no more needed now.
NVGPU-4690
Change-Id: Iee556feed4a25902faba87a606418861185e4089
Signed-off-by: Abdul Salam <absalam@nvidia.com >
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
6974f784e2
gpu: nvgpu: Update cbc_init_support() return error
...
Currently, nvgpu_cbc_init_support() doesn't return error if
cbc.alloc_comptags() fails. Modify nvgpu_cbc_init_support() to check
error returned by cbc.alloc_comptags(). If alloc_comptags() fails, free
allocated cbc memory and set cbc pointer to NULL.
JIRA NVGPU-4666
Change-Id: Id7edaeebc81e7d7029d98bcdbffaf6506c8f0979
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
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2020-12-15 14:13:28 -06:00
Thomas Fleury
4f682bf107
gpu: nvgpu: igpu and dgpu driver libs
...
Different build flags are used for iGPU and dGPU in
safety build. In order to support dGPU in unit tests,
a separate library is needed for the driver.
Added makefiles to build:
- libnvgpu-drv-igpu.so
- libnvgpu-drv-dpgu.so
Updated scripts and units makefiles to use libnvgpu-drv-igu
by default.
Jira NVGPU-5217
Change-Id: Ibcc56088723cec5cb2d0ac42725102ae0c886014
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
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2020-12-15 14:13:28 -06:00
Abdul Salam
88d3640bc5
gpu: nvgpu: Refacotor clk_domain Unit
...
As a part of refactoring this patch does the following
*Move local struct to unit specific header file
*Move nvgpu_pmu_clk_domain_freq_to_volt from clk.c to
clk_domain.c
*Move PMU specific struct to ucode_clk_inf.h
*Merge content from nvgpu/clk.h to pmu/clk/clk.h
*Update yaml file
This will help to have arch consistency across all units.
Change-Id: Ied5c6ee637e7fd5bbdee3f5bc3f6cf216454428a
Signed-off-by: Abdul Salam <absalam@nvidia.com >
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2020-12-15 14:13:28 -06:00
Divya Singhatwaria
f0896f94e1
gpu: nvgpu: Add falcon gops
...
Add falcon gops for accessing below constants. This is
required for nvgpu-next.
falcon_falcon_dmemc_blk_m
falcon_falcon_imemc_blk_f
JIRA NVGPU-4834
Change-Id: I1a60f473470a7a03fb31dceecfccd91fcc690de9
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com >
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2020-12-15 14:13:28 -06:00
Divya Singhatwaria
c060e754fc
gpu: nvgpu: ELPG dump stats at shutdown
...
ELPG_DISALLOW command fails during gk20a shutdown.
It was due to nvgpu_can_busy() which was returning
0 before without acknowledging the ELPG_DISALLOW
command.
Since the system is shutting down so fix this issue
by setting the ACK for disallow command without
waiting for actual ACK from PMU.
In doing so the state machine is also maintained
properly and the driver does not dump fail stats.
BUG 200588696
Change-Id: I943d8e6108fa0f9c418ccb1a7f061307823f1ec6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com >
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
9bee2fe660
gpu: nvgpu: prealloc priv cmdbuf metadata
...
Move preallocation of priv cmdbuf metadata structs to the priv cmdbuf
level and do it always, not only on deterministic channels. This makes
job tracking simpler and loosens dependencies from jobs to cmdbuf
internals. The underlying dma memory for the cmdbuf data has always been
preallocated.
Rename the priv cmdbuf functions to have a consistent prefix.
Refactor the channel sync wait and incr ops to free any priv cmdbufs
they allocate. They have been depending on the caller to free their
resources even on error conditions, requiring the caller to know how
they work.
The error paths that could occur after a priv cmdbuf has been allocated
have likely been wrong for a long time. Usually the cmdbuf queue allows
allocating only from one end and freeing from only the other end, as
that's natural with the hardware job queue. However, in error conditions
the just recently allocated entries need to be put back. Improve the
interface for this.
[not part of the cherry-pick:] Delete the error prints about not enough
priv cmd buffer space. That is not an error. When obeying the
user-provided job sizes more strictly, momentarily running out of job
tracking resources is possible when the job cleanup thread does not
catch up quickly enough. In such a case the number of inflight jobs on
the hardware could be less than the maximum, but the inflight job count
that nvgpu sees via the consumed resources could reach the maximum.
Also remove the wrong translation to -EINVAL from err from one call to
nvgpu_priv_cmdbuf_alloc() - the -EAGAIN from the failed allocation is
important.
[not part of the cherry-pick: a bunch of MISRA mitigations.]
Jira NVGPU-4548
Change-Id: I09d02bd44d50a5451500d09605f906d74009a8a4
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329657
(cherry picked from commit 25412412f31436688c6b45684886f7552075da83)
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2020-12-15 14:13:28 -06:00
Thomas Fleury
bc4f74d854
gpu: nvgpu: add pg209 sku device id
...
Jira NVGPU-5375
Change-Id: I745832b3bd1865abaca24b4b96fd174097542427
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333424
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2020-12-15 14:13:28 -06:00
Thomas Fleury
85b9c98eba
gpu: nvgpu: init hal for nvgpu-next dgpu
...
Add hooks for nvgpu-next dgpu init hal.
Jira NVGPU-5382
Change-Id: I5395a32ceda21b43b186756ba6dd5937251c3548
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
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2020-12-15 14:13:28 -06:00
Seema Khowala
68caee196a
gpu: nvgpu: add mm.mmu_fault.parse_mmu_fault_info gops
...
Add mm.mmu_fault.parse_mmu_fault_info gops. This is required
for nvgpu-next.
Also add mmu_engine_id type in mmu_fault structure. This variable
will be set in parse_mmu_fault_info hal so that
gv11b_mm_mmu_fault_handle_other_fault_notify does not depend
upon any chip specific h/w header. This is needed because
BAR2 mmu engine id has changed in nvgpu-next.
JIRA NVGPU-5032
Change-Id: I0c5e9ef607aff5b105f59582013cbfb31396290a
Signed-off-by: Seema Khowala <seemaj@nvidia.com >
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2020-12-15 14:13:28 -06:00
Thomas Fleury
91401cc849
gpu: nvgpu: build flag for dGPU in safety
...
CONFIG_NVGPU_DGPU already exists to enable dGPU support.
Replace NVGPU_FORCE_DGPU_SAFETY_PROFILE with CONFIG_NVGPU_DGPU.
Jira NVGPU-5277
Change-Id: Ia1617a42269b18c1a443d91f9ca2ba38afd4a6f9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2322899
(cherry picked from commit 9882b44709ef472b9113e3cd43974fe177eeeb24)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
6fc1e41150
gpu: nvgpu: split submit on deterministic
...
Avoid repetitive branching on the c->deterministic flag and on build
time flags by breaking the submit function on the runtime flag into two
functions of which one gets called.
In deterministic mode the job tracking conditions are simpler, there are
a few extra prechecks to guarantee deterministic latency and the
railgate corner case, and deferred cleanup is never done.
In nondeterministic mode job tracking has more conditions, a power
reference is taken for the job lifetime, and deferred cleanup is
assumed.
These two paths still share some common code. Split it to two more
functions to act as easy building blocks so that the main logic is
apparent.
Jira NVGPU-4548
Change-Id: I64f91dcf09acb16f409dc04a12ad1e144d0cce56
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333728
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
b077c6787d
gpu: nvgpu: split sync and gpfifo work in submit
...
Make the big submit function somewhat shorter by splitting out the work
to do job allocation, sync command buffer creation and gpfifo writing
out to another function. To emphasize the difference between tracked and
fast submits, add two separate functions for those two cases.
Jira NVGPU-4548
Change-Id: I97432a3d70dd408dc5d7c520f2eb5aa9c76d5e41
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
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2020-12-15 14:13:28 -06:00
Antony Clince Alex
96bea78d55
gpu: nvgpu: add init_hw, intr_enable hals to ce gops
...
Add following two HALs to ce gops:
- init_hw:
Build a list of non-stall interrupt vectors and register them
with struct nvgpu_mc.
- intr_enable:
Enable ce engine stall, non-stall interrupts.
Jira: NVGPU-5034
Change-Id: Ibdc768c2bce778237233803ebbbd5190362b4578
Signed-off-by: Antony Clince Alex <aalex@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329166
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2020-12-15 14:13:28 -06:00
ajesh
1500ce829a
gpu: nvgpu: assert for OS API errors in non fusa
...
Handle the OS API errors with assert in non FUSA builds also.
Jira NVGPU-4987
Change-Id: I90428e845ae9f934b0d4bce08ab93f13f3fde2f8
Signed-off-by: ajesh <akv@nvidia.com >
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2020-12-15 14:13:28 -06:00
Abdul Salam
af3311ddea
gpu: nvgpu: Refactor clock_domain unit
...
As a part of refactoring move nvgpu_clk_domain struct from public
to private.
This will help to have arch consistency across all units.
Use public functions to fetch the data across other units.
The following functions are added to access data in clk_domain unit.
*nvgpu_pmu_clk_domain_get_f_points()--> To get freq points
*nvgpu_pmu_clk_domain_update_clk_info() --> To update change seq script
with clock domain data
NVGPU-4689
Change-Id: Idc85e3cf5bbe1b80766ce6c9f07b3305ef04cbdc
Signed-off-by: Abdul Salam <absalam@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332185
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2020-12-15 14:13:28 -06:00
Seema Khowala
aff5497907
gpu: nvgpu: add intr_unit_bitmask i/p param for fb.intr.isr
...
tu104 onwards, fb interrupt status/enable/disable moved from
fb_niso_intr_* reg to fb_*vector* registers.
At the top level, fb interrupt status/enable/disable is done
using hub_intr bit in mc_intr registers.
Starting nvgpu-next, this has changed.
JIRA NVGPU-5032
Change-Id: Ib54170b055b83e2696312c811c2e3ba678749359
Signed-off-by: Seema Khowala <seemaj@nvidia.com >
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2020-12-15 14:13:28 -06:00
Thomas Fleury
091e4b9396
gpu: nvgpu: detect enabled ecc units in hal init
...
ECC scrubbing can start before GPU characteristics
are initialized. Detect enabled ECC units in HAL
init functions so that scrubbing is started properly.
Bug 2919887
Change-Id: Ic20b4223504a947eed78418779531e26c2116d41
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2330101
(cherry picked from commit e8d380d7bba91b895033ebb5ab0d281be6d3db30)
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2020-12-15 14:13:28 -06:00
Seeta Rama Raju
e0cb334f4e
gpu: nvgpu: Add fault injection variable for devctl_channel unit
...
JIRA NVGPU-5232
Change-Id: Ia0dde3390d0dc8c34f02e7a99419c0907213a2ed
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331323
(cherry-picked from commit bdd370e80375527566cd6148812456d4369725b2)
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2020-12-15 14:13:28 -06:00
Tejal Kudav
25461c7621
gpu: nvgpu: Move nvlink HAL code to /hal
...
Remove the nvlink register read/write code from /common.
Move the register handling code to /hal and add
HALs to to expose this functionality to common code.
JIRA NVGPU-2964
Change-Id: Iafba9f4e29cc0f1130dbf5dd14fbbf8b6b5bb8ec
Signed-off-by: Tejal Kudav <tkudav@nvidia.com >
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
3378fbbb49
gpu: nvgpu: remove old ALLOC_GPFIFO
...
NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO has not been used in years. Delete it.
The SUBMIT_BIND (and ALLOC_GPFIFO_EX before it) ioctl shall be used
instead.
Jira NVGPU-4548
Change-Id: If707c1b131386d3662815518cd3689b596db5330
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325788
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2020-12-15 14:13:28 -06:00
Sagar Kamble
9f8d5acfbb
gpu: nvgpu: fix the return value from gk20a_mm_pin
...
The return value in case of failure of dma_buf_attach and
dma_buf_map_attachment was ignored and NULL was returned.
This would lead to following null pointer access. Fix it.
[ 293.622880] Unable to handle kernel NULL pointer dereference
at virtual address 0000000000000000
...
[ 293.711860] Hardware name: quill (DT)
[ 293.720393] pc : nvgpu_linux_sgt_create+0x14/0xa8 [nvgpu]
[ 293.725871] lr : nvgpu_vm_map_linux+0x104/0x1c8 [nvgpu]
...
[ 293.813934] Call trace:
[ 293.816455] nvgpu_linux_sgt_create+0x14/0xa8 [nvgpu]
[ 293.821573] nvgpu_vm_map_linux+0x104/0x1c8 [nvgpu]
[ 293.826515] nvgpu_vm_map_buffer+0x120/0x290 [nvgpu]
[ 293.831542] gk20a_as_dev_ioctl+0x364/0xfb8 [nvgpu]
[ 293.836416] ksys_ioctl+0x17c/0xba8
[ 293.839899] __arm64_sys_ioctl+0x18/0x28
[ 293.843817] do_el0_svc+0xf8/0x1b8
[ 293.847214] el0_sync_handler+0x11c/0x28c
[ 293.851217] el0_sync+0x140/0x180
Bug 2834141
Change-Id: I0d9e863d0326946c8091bfb1b907b62b055f7272
Signed-off-by: Sagar Kamble <skamble@nvidia.com >
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2020-12-15 14:13:28 -06:00
Debarshi Dutta
8e9d837fd5
gpu: nvgpu: remove unused include file
...
#include "../../../arch/arm/mach-tegra/iomap.h" should be removed.
Bug 2887230
Change-Id: I3402dbae5a61845475cff4a0a9a36c60f41b45cd
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com >
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2020-12-15 14:13:28 -06:00
Vinod G
bb93223a21
gpu: nvgpu: add check_warp_esr_error hal
...
Set check_warp_esr_error hal pointer to
gv11b_gr_check_warp_esr_error hal function.
Jira NVGPU-4867
Signed-off-by: Vinod G <vinodg@nvidia.com >
Change-Id: Ib014c5ff2456836af2fe89f849f37991fe52844e
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2020-12-15 14:13:28 -06:00
Seema Khowala
d013e42f60
gpu: nvgpu: rename INTR_* defines
...
Rename INTR_* to MC_INTR_* defines.
JIRA NVGPU-5032
Change-Id: Iee291e2003171e3cf02b6452f1567747093e5773
Signed-off-by: Seema Khowala <seemaj@nvidia.com >
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2020-12-15 14:13:28 -06:00
ajesh
b6c7b9976e
Revert "gpu: nvgpu: modify the prints for return values"
...
This reverts commit 48946d43fd9b6028900b594d329cd7f51f196ba4.
Jira NVGPU-4987
Change-Id: I2fbaa3ff0b5eec7fbf051353a6bd80576e818f2e
Signed-off-by: ajesh <akv@nvidia.com >
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2020-12-15 14:13:28 -06:00
Vinod G
8f3a0f4486
gpu: nvgpu: add sm rams ecc enabled flag
...
Add sm rams ecc enabled flag.
Move ecc scrubbing timeout defines to
gr_init_gv11b.h
Jira NVGPU-4871
Signed-off-by: Vinod G <vinodg@nvidia.com >
Change-Id: Ie43f5947c53be697d0b2fd064d308612856d823a
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2020-12-15 14:13:28 -06:00
Rajesh Devaraj
bfa1736351
gpu: nvgpu: update bug() to print function name
...
This patch updates BUG() to print the name of the function that
triggered it. In addition, it also prints the line number in which
BUG() is present in the function that triggered SW quiecese. This
will aid in finding the function due to which SW quiesce has been
triggered.
Bug 2919887
Change-Id: Ie63d9e5f1ba128da54ddc18bd259659d634b60cb
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329796
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
dd2fb50a1a
gpu: nvgpu: require deferred cleanup for aggressive sync destroy
...
Aggressive sync destroy is used on some platforms where the amount of
syncpoints is limited. It can cause sync objects to get allocated and
freed in the submit path and when jobs are cleaned up, so require
deferred cleanup. Allocations do not belong to job tracking in a
deterministic submit path.
Although this has been technically allowed before, deterministic
channels have likely not been a priority on those old platforms with
aggressive sync destroy set.
Update virtualized gp10b platform data to match on a gp10b-vgpu compat
string instead of gk20a-vgpu. gk20a (Tegra T124) hasn't been supported
for a long time. Delete the aggressive sync destroy field from this
platform. It's got enough syncpoints to not dynamically allocate them;
having this property set for gp10b-vgpu has likely been a mistake.
This is not a completely pure cherry-pick: also extend the gpu
characteristics to not advertise full deterministic submit support when
aggressive sync destroy is off. This platform flag cannot be adjusted by
the user unlike many other flags.
Jira NVGPU-4548
Change-Id: I283f546d48b79ac94b943d88e5dce55710858330
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2322042
(cherry picked from commit b1ba2b997b2174e365bcb0782ef3e67260ff9e57)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
2001b8ec97
gpu: nvgpu: remove aggressive sync init from platform
...
Remove the boolean aggressive_sync_destroy flag from struct
gk20a_platform; only the threshold to set the channel limit is useful in
the platform data. The boolean flag is a runtime condition and it always
starts as false.
Jira NVGPU-4548
Change-Id: I1a4b9903978ab239581857ff791a7983f59fdc13
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331357
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
0b70fff5db
gpu: nvgpu: fix job count calculation for non-pow2
...
The CIRC_SPACE and CIRC_CNT macros work as expected when the buffer size
is a power of two. The userspace-supplied number of inflight jobs is not
necessarily so. Compare the get and put pointers manually.
Jira NVGPU-4548
Change-Id: Ifa7bd6d78f82ec8efcac21fcca391053a2f6f311
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328572
(cherry picked from commit 33dffa1cfb142eea0f28474566c31b632eee04f5)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
47c3d4582c
gpu: nvgpu: hide priv cmdbuf gva and size
...
Add an accessor function in the priv cmdbuf object for gva and size to
be written in a gpfifo entry once the cmdbuf build is finished. This
helps in eventually hiding the struct priv_cmd_entry as an
implementation detail.
Add a sanity check to verify that the buffer has been filled exactly to
the requested size. The cmdbufs are used to hold wait and increment
commands for syncpoints or gpu semaphores. A prefence buffer can hold a
number of wait commands of equal size, and the postfence buffer holds
exactly one increment.
Jira NVGPU-4548
Change-Id: I83132bf6de52794ecc419e033e9f4599e488fd68
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325102
(cherry picked from commit d1831463a487666017c4c80fab0292a0b85c7d83)
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2020-12-15 14:13:28 -06:00
Dinesh
1c1da3d6b4
gpu: nvgpu: Syncpoint invalid value to ~0.
...
As qnx syncpoint's invalid value is ~0, change the code
to handle this.
Bug 200603716
Change-Id: I5ec79688cd9e60066725781f1effe57692ec0c27
Signed-off-by: Dinesh <dt@nvidia.com >
(cherry picked from commit 705260565a75bc90683841c4c08e4c857bda39f0)
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2020-12-15 14:13:28 -06:00
Debarshi Dutta
c1521a7bba
gpu: nvgpu: change system suspend's implementation
...
Currently, for platforms with canRailgate device characteristics disabled,
suspend can block as deterministic channels hold busy references. This
patch makes the change to first hold off any new jobs for deterministic
channels and then reverts back the busy references taken by those
channels. Following this, suspend also waits for the device to get idle
by waiting (with timeout) for the nvgpu's internal usage counter to be
come zero. This ensures there are no further jobs in progress and
allows the system to go into a suspend state.
Bug 200598228
Bug 2930266
Change-Id: Id02b4d41a9c2dd64303b2e2449dbed48c12aea4c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328489
(cherry picked from commit 9d1e07ca18https://git-master.nvidia.com/r/c/linux-nvgpu/+/2330159
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
e9747d5477
gpu: nvgpu: remove wait_fence_fd from incr_user
...
The wait_fence_fd parameter in nvgpu_channel_sync_incr_user() has not
been used since commit 1a4647272fkholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2326604
(cherry picked from commit f8031142270fb87ac41597ae70a80505078ae6d5)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
aa1322f975
gpu: nvgpu: move syncpt priv cmd allocation
...
channel_sync_syncpt_gen_wait_cmd() is rather simple now and is called
from two places where one has the buf preallocated and the other
doesn't. Remove the preallocated flag from the function, moving the
allocation to the single place where it is needed.
Jira NVGPU-4548
Change-Id: I48083f4f6f1093d64b67c63582291392a3481932
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325101
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2020-12-15 14:13:28 -06:00
