Seshendra Gadagottu
587a7b1e93
gpu: nvgpu: gp10b: update headers
...
Update replayable page fault fifo, interrupt and bar2 block
headers.
Bug 1587825
Change-Id: Ifa0d3b640bdd5f3f6fbc7826c1d1edba494340df
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com >
Reviewed-on: http://git-master/r/661117
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com >
2016-12-27 15:22:03 +05:30
Terje Bergstrom
4493b6b200
gpu: nvgpu: gp10b: Enable CILP mode for compute
...
Allow enabling CILP for compute. Set CTA by default.
Bug 1517461
Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com >
Reviewed-on: http://git-master/r/661298
GVS: Gerrit_Virtual_Submit
2016-12-27 15:22:03 +05:30
Terje Bergstrom
15839d4763
gpu: nvgpu: Implement gp10b context creation
...
Implement context creation for gp10b. GfxP contexts need per channel
buffers.
Bug 1517461
Change-Id: Ifecb59002f89f0407457730a35bfb3fe988b907a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com >
Reviewed-on: http://git-master/r/660236
2016-12-27 15:22:03 +05:30
Terje Bergstrom
07b7a534fa
gpu: nvgpu: Synchronize gp10b headers with gm20b
...
Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.
Bug 1567274
Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com >
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit
2016-12-27 15:22:02 +05:30
Ken Adams
dfdd5ba3cb
gpu: nvgpu: gp10b headers
...
first cut. just to get started...
Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d
Signed-off-by: Ken Adams <kadams@nvidia.com >
Reviewed-on: http://git-master/r/447753
2016-12-27 15:22:01 +05:30
