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1353 Commits

Author SHA1 Message Date
Divya
943eb77b20 gpu: nvgpu: add pmu HALs 
Add following PMU Hals:

- get_pmu_msgq_head
- set_pmu_msgq_head
- set_pmu_new_instblk

JIRA NVGPU-9758

Change-Id: Iba1e37a299309e0e31970a8fbdf248d662bd759b
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2906872
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-06-08 10:49:35 -07:00
Ramalingam C
ad320f60b9 gpu: nvgpu: sema based gpfifo submission tracking 
Implement a hw semaphore which is used to track the gpfifo submission.
This is implementation used when the userd.gp_get() is not defined and
also the feature flag NVGPU_SUPPORT_SEMA_BASED_GPFIFO_GET is set.

At the end of each job submitted, submit a semaphore to write the
gpfifo get pointer at hw semaphore addr. At next job submission
processing we will read the gpfifo.get from the designated hw semaphore
location.

JIRA NVGPU-9588

Change-Id: Ic88ace1a3f60e3f38f159e1861464ebcaea04469
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2898143
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Tested-by: Martin Radev <mradev@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-06-08 10:44:37 -07:00
Santosh BS
be5312cb9b gpu: nvgpu: falcon2/riscv update for multimedia 
- Define falcon ID for OFA and NVJPG
- Initialize falcon sw for OFA and NVJPG
- Program boot_vector before riscv kick-start

Jira NVGPU-9429
Bug 3962979

Change-Id: If6e63cb1e99ada3742b708bb0f8f7edc64366318
Signed-off-by: Santosh BS <santoshb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2913882
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-06-07 22:09:04 -07:00
Divya
912cb15999 gpu: nvgpu: add pmu hals 
Add following PMU hals:

- pmu_get_mutex_reg
- pmu_set_mutex_reg
- pmu_get_mutex_id
- pmu_get_mutex_id_release
- pmu_set_mutex_id_release

JIRA NVGPU-9758

Change-Id: Ic73ad8a9e07defadeb49a2ca3440fe000203a42f
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2904414
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-31 18:43:04 -07:00
Rajesh Devaraj
f1613a300b gpu: nvgpu: add get_cbm_alpha_cb_size hal 
Add get_cbm_alpha_cb_size hal to avoid duplication of code to new chips.

Bug 4134898

Change-Id: I59fe7065b142b3296bfa3b20cb3198ac1ec859ce
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2911335
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-31 01:51:34 -07:00
Santosh BS
3407c01357 gpu: nvgpu: gops declaration for multimedia engines 
- gops struct declaration for nvenc, ofa, nvdec and nvjpg
- minor refactoring with struct nvgpu_nvenc

Jira NVGPU-9429
Bug 3962979

Change-Id: I888c6bd571554f18f2e9ca2adfaaacd1a8286ed0
Signed-off-by: Santosh BS <santoshb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2908521
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-29 04:01:46 -07:00
atanand
4b2e1b4a38 gpu: nvgpu: Print PC and ESR for GR errors when fault occurs 
Added print for PC, WARP and GLOBAL ESR when the fault occurs.

Bug 3973433

Change-Id: I8ec1d2aa16125d1628ca7321629b9f771322268a
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2900112
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-22 19:15:08 -07:00
Divya
ef1fb41e54 gpu: nvgpu: add pmu hals to resolve mismatch 
Add the following HALs to avoid the duplication
of code for future chips:
- set_mailbox1
- get_ecc_address
- get_ecc_status
- set_ecc_status

JIRA NVGPU-9758

Change-Id: I54ce3dfaae2873dbcd88edabbd877eca9f3d1fdb
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2898016
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-16 06:27:08 -07:00
Austin Tajiri
7522c3ee31 gpu: nvgpu: skip security check in ctxsw init 
Force ctxsw ucode to skip the security level check by clearing mailbox 1
before starting FECS/GPCCS.

Jira NVGPU-9217

Change-Id: Id4286d0882a29a849128e62c5421c8ae6071e3b1
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2891013
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-15 06:07:23 -07:00
Austin Tajiri
7e0351f291 gpu: nvgpu: retry MMU fault buffer read 
When handling MMU faults, retry the first MMU fault buffer read multiple
times until it contains valid data. There may be a delay between the MMU
fault interrupt triggering and the fault buffer containing valid data.

Jira NVGPU-9217

Change-Id: I06b442acaf54a4e036795de65345b423f9b424bf
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2881909
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-15 06:07:18 -07:00
Rajesh Devaraj
a321679a5d gpu: nvgpu: add is_gsp_supported flag 
This patch adds is_gsp_supported flag and initializes it for GA10B,
TU104. Further, this flag is checked before initializaing GSP LITE
falcon.

JIRA NVGPU-9983

Change-Id: If0a4a3095c15cac113895f3d114e731f35211c5d
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2902651
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-15 01:19:26 -07:00
Divya
a4175b1265 gpu: nvgpu: resolve pmu mismatches 
Add the following pmu HALs for PMU registers
to avoid duplication of code for future chips:
- get_bar0_addr
- get_bar0_data
- get_bar0_timeout
- get_bar0_ctl
- get_bar0_error_status
- set_bar0_error_status
- get_bar0_fecs_error
- set_bar0_fecs_error
- get_mailbox
- get_pmu_debug

JIRA NVGPU-9758

Change-Id: If8b9c91ecd51d526babf12e3cee09048d736f0f4
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2897156
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-05 19:48:04 -07:00
Rajesh Devaraj
01d3ed09b0 gpu: nvgpu: update get_access_map 
This patch re-names the variables used in gr_init_get_access_map API:
whitelist - gr_access_map
num_entries - gr_access_map_num_entries
wl_addr_*[] - gr_access_map_*[]

JIRA NVGPU-9849

Change-Id: I3a0a59410af8983867af5bc2f9ff200e56e190c4
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2891567
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-05 02:31:10 -07:00
Shashank Singh
9512b9f1de gpu: nvgpu: remove user managed addr space capability flag 
Remove NVGPU_GPU_IOCTL_ALLOC_AS_FLAGS_USERSPACE_MANAGED and
NVGPU_AS_ALLOC_USERSPACE_MANAGED flags which are used for supporting
userspace managed address-space. This functionality is not implemented
fully in kernel neither going to be implemented in near future.

Jira NVGPU-9832
Bug 4034184

Change-Id: I3787d92c44682b02d440e52c7a0c8c0553742dcc
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2882168
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-04 11:39:30 -07:00
Divya
b54cb9fd97 gpu: nvgpu: add pmu hals 
Add the following HALs for following PMU registers:
- get_irqstat
- set_irqsclr
- set_irqsset
- get_exterrstat
- set_exterrstat
- get_exterraddr

JIRA NVGPU-9758

Change-Id: Ib153d3189ff493fdb726ec2d1e81b863476fc667
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2886108
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-21 11:33:56 -07:00
Martin Radev
81d95456b9 gpu: nvgpu: Rename PLATFORM_ATOMIC to SYSTEM_COHERENT 
To support current and future usecases, it would be
beneficial to select the SYSTEM_COHERENT aperture explicitly.

The benefits are:
- platform atomic code is cleaned-up.
- userspace can select the SYSTEM_COHERENT aperture for any
  specific usecases.

Bug 3959027

Change-Id: I6489ebe87fa75cc760930277bad5e0cacca80eb6
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864177
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-21 11:31:53 -07:00
Austin Tajiri
24bebfabaf gpu: nvgpu: add engine base vector HALs 
Add HALs for getting the base vectors for stall and nonstall engine
interrupts. The engine interrupt IDs are added to these base vectors
to determine the engine stall and nonstall interrupt vectors.

Jira NVGPU-9217

Change-Id: Ieaf0e75caac0f7e23684b80466fbf1dc3a57f68d
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2880426
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-13 22:16:13 -07:00
Austin Tajiri
56a4680a3b gpu: nvgpu: refactor gr.intr.handle_sw_method 
- Add defintions of the gfx/compute classes and methods that are
  generated from the hw/sw class header files. Use these definitions
  instead of the hard-coded ones so that mismatches may be caught by
  the HAL checker.
- Abstract out the sw method handling functionality of
  gr.intr.handle_sw_method into gr.intr.handle_gfx_sw_method and
  gr.intr.handle_compute_sw_method and have gr.intr.handle_sw_method
  call these two new HALs.

Jira NVGPU-9217

Change-Id: Ia30fcba6174878d9b5b7b5910c564c879a702ddc
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2885547
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-13 12:20:33 -07:00
Divya
7a4fff4b17 gpu: nvgpu: add hal for pmu sequence cleanup 
- On older chips, PMU uses CMD-MSG queue method to
  communicate with NvGPU.
- From Turing onwards, PMU uses RPC method for this.
- During poweroff, we release pmu_sequence and reset the
  members of the structure.
- For chips that use RPC, we need to free the payload as well
  and then reset the members.
- Add pmu_seq_cleanup hal for this.

Bug 4019694
Bug 4059157

Change-Id: Ieb474fe4ed81f54d78480214cde53b51d45652c6
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2882267
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-12 16:28:52 -07:00
Austin Tajiri
7cab0e7124 gpu: nvgpu: add ltc.intr.retrigger HAL 
Add an ltc.intr.retrigger HAL for chips that need to retrigger pending
interrupts in the LTC ISR.

Jira NVGPU-9217

Change-Id: I1fe74c2f72afc7cf852cf0d273c7a8f8652a53c9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869902
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:26 -07:00
Austin Tajiri
db22d49239 gpu: nvgpu: add LTC interrupt register HALs 
Add HALs for reading and writing LTC interrupt configuration registers.

Jira NVGPU-9217

Change-Id: I2d3a913ae5e69009d7888495af9b79acb4960ac9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869901
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:20 -07:00
Austin Tajiri
b1ac11e0e0 gpu: nvgpu: add ltc.intr.handle_illegal_compstat HAL 
Add ltc.intr.handle_illegal_compstat to handle the case in which a chip
does not support the ILLEGAL_COMPSTAT LTC interrupt.

Jira NVGPU-9217

Change-Id: I40ddcbda6176ffa36037bd1998af4ec1bed67ec9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869900
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:14 -07:00
Austin Tajiri
3a69b445fc gpu: nvgpu: fix MMU fault register mismatches 
Fix the following MMU register mismatches by using the appropriate HALs
when possible:
 - fb_mmu_fault_status_r
 - fb_mmu_debug_ctrl_r

Jira NVGPU-9217

Change-Id: I3380ac449f20f2ce47b439303b9abd19010e6b26
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869899
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:08 -07:00
Austin Tajiri
f2ce282b7e gpu: nvgpu: add HALs for ECC interrupt handling registers 
Add HALs for reading ECC status, retrieving ECC error info, and clearing
ECC errors. Use these HALs in place of direct register access in
GV11B/GA10B ECC interrupt handlers.

Jira NVGPU-9217

Change-Id: I792f05ede5576b958b678bc5eb8f2b8dc5e7c4d7
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869898
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:03 -07:00
Sagar Kamble
53dc53a8b4 gpu: nvgpu: add hal to get the bar2 vm size 
On ga10b+ platforms, more VM space is needed to map various buffers
to bar2 vm. Engine method buffer is mapped for each pbdma and for
maximum supported TSGs this requires more than 32MB of space.
Also we need to consider fault buffer space and vab buffer
space requirement.

Bug 3958581

Change-Id: I9ee87119f762352ee12859b71c08a5f75b3554e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872811
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-25 02:45:47 -07:00
Santosh BS
2a865e3aad gpu: nvgpu: NVENC support on TU104 
This patch adds nvenc support for TU104
- Fetch engine/dev info for nvenc
- Falcon NS boot (fw loading) support
- Engine context creation for nvenc
- Skip golden image for multimedia engines
- Avoid subctx for nvenc as it is a non-VEID engine
- Job submission/flow changes for nvenc
- Code refactoring to scale up the support for other multimedia
  engines in future.

Bug 3763551

Change-Id: I03d4e731ebcef456bcc5ce157f3aa39883270dc0
Signed-off-by: Santosh BS <santoshb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859416
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-24 17:07:49 -07:00
vivekku
d5e00ef380 gpu: nvgpu: hal: enable gsp scheduler 
- enable gsp scheduler for orin silicon platforms
- disabled gsp scheduler for simulation and enabled KMD scheduler

Bug 3935433

Change-Id: I38cb35937ffb25b76fbf37fa4eeb9e993f0370c5
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872897
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-21 02:38:01 -07:00
Richard Zhao
f791adf880 gpu: nvgpu: move .runlist.hw_submit to use runlist_id 
Use detailed function parameters runlist_id, iova/aperture and count, so
the HAL could be reused on server side.

Jira GVSCI-15773

Change-Id: I28f68682b9eea4e798af5c850c87840bd9b79970
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863444
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-21 02:31:29 -07:00
Richard Zhao
da1da8f563 gpu: nvgpu: move .preempt_trigger/.is_preempt_pending to IDs 
.preempt_tsg uses .preempt_trigger/.is_preempt_pending, so they both
have to use runlist_id and tsgid too.

Jira GVSCI-15770

Change-Id: Ida24d160c362ea1348d7c19e6d0352bb390d0a64
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863442
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-21 02:30:57 -07:00
Richard Zhao
8f5adab299 gpu: nvgpu: .preempt_tsg move to use runlist_id/tsgid 
It's for making .preempt_tsg reusable on server side.

Jira GVSCI-15770

Change-Id: Id9f477baa29cb63fb0e1d1650f4b1e6a2fa248c0
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863441
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-21 02:30:49 -07:00
Richard Zhao
41823694a3 gpu: nvgpu: add .init_golden_image HAL 
golden image is created differently on native and VF.

Jira GVSCI-15772

Change-Id: I8d78d1214d8aac1d39d6529b68adef1dd6f8a516
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863440
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-17 04:04:33 -07:00
atanand
9dd2a8fc73 gpu: nvgpu: Get GA10B EMC floorsweeping status 
The memory bandwidth reported by the nvgpu driver is a resultant of FBP and EMC floorsweeping status. The FBP floorsweep status was already getting reported in the GPU characterstics so the status of EMC was fetched and reported in this change.

Jira NVGPU-9609
Bug 3661074

Change-Id: Ia2fe6cb029d086765da15d9e964ea77256e06604
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859237
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-17 04:00:00 -07:00
vivekku
eb52414f22 gpu: nvgpu: ga10b: disable gsp scheduler 
Changes:
- disabling gsp scheduler

Bug 3935433

Change-Id: Iedb049b0ad1f052e8b3d1692d9280e80dcee9163
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869839
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-17 03:56:24 -07:00
prsethi
6b2c080f8f gpu:nvgpu: add enable flag for KMD_SCHEDULING_WORKER_THREAD support 
Currently KMD_SCHEDULING_WORKER_THREAD can be enabled/disabled using
compile time flag but this flag does give ability to control the
feature based on the chip.
GSP is enabled only on ga10b where KMD_SCHEDULING_WORKER_THREAD should
be disabled while should be enabled for other chips at the same time
to support GVS tests.
Change adds enabled flag to control KMD_SCHEDULING_WORKER_THREAD based
on the chip.

Bug 3935433

Change-Id: I9d2f34cf172d22472bdc4614073d1fb88ea204d7
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2867023
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-17 03:55:02 -07:00
Richard Zhao
84ddb23633 gpu: nvgpu: move .force_ctx_reload to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Id4e815e9cf78a43156449d0e77e8e331fc906725
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863439
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:56:10 -07:00
Richard Zhao
c8d6a91de6 gpu: nvgpu: update .channel.enable/disable to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Ibd94ab8c9f0492bd6d20243525905d637eb8de66
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863438
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:56:04 -07:00
Richard Zhao
d9c8d317f0 gpu: nvgpu: update .read_state to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Ia5e30ebb0e8092b9cdc4c3f3cd524f585fd4b410
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863437
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:58 -07:00
Richard Zhao
2ff110f722 gpu: nvgpu: update .clear to use runlist_id and chid 
- Moving to use IDs rather than struct makes it reusable on server side.
- move channel bind/unbind to use .enable/.clear HALs

Jira GVSCI-15770

Change-Id: I86d4aae2953024e537e32a35fe9cabb1b91cd201
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863436
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:53 -07:00
Richard Zhao
a7d358f773 gpu: nvgpu: vf: init gmmu related structure 
vf driver implements gmmu map/unmap on client side.

- adds helper function to check whether nvgpu device is vf or legacy
vgpu.
- inits pd_cache struct for vf
- inits platform->phys_addr for ipa2pa

Jira GVSCI-15733

Change-Id: I46c84f0acdd167b9c4bdcec2f1c25f3acd6a0f71
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863430
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:47 -07:00
Richard Zhao
de0e1be1ed gpu: nvgpu: add g->func_regs 
rework nvgpu_func_* io accessors to use g->func_regs rather than use
g->regs. g->regs is invalid for VF.

Jira GVSCI-15732

Change-Id: I71e788ff135c5a286b273c151e1bd0a88e9d61e2
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863429
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:41 -07:00
Kishan
a765a76c81 gpu:nvgpu: Expose physical gpc,tpc layout for ecc sysfs nodes. 
Added new gr_config member to hold TPC physical id map.
Updated ecc stats structures to hold physical gpc,tpc
numbers. Previously logical id's were exposed via ecc
sysfs nodes.
Consumers of ecc sysfs nodes refer tpc_fs_mask which is
physical gpc/tpc layout whereas ecc sysfs nodes were updated
with logical gpc/tpc layout. This change ensures that both
use the same framework.

JIRA NVGPU-9607
Bug 3950378

Change-Id: I1f91956dd027ffdc12042dd33dc491a3ce1e1ff6
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2866264
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-08 06:32:00 -08:00
Sagar Kamble
2acfb55780 gpu: nvgpu: fix tex rd coalesce disable logic 
NETLIST_REGIONID_SW_CTX_LOAD writes update gr_gpcs_tpcs_tex_m_dbg2_r to
default value that keeps rd coalesce enabled for LG & SU.

Disable rd coalesce for tex, lg and su after NETLIST_REGIONID_SW_CTX_LOAD
writes during gr init and golden ctx init for it to take effect.

For gr sw method handling, don't update the tex rd coalesce on interrupt
with offset *_SET_RD_COALESCE as we want to keep rd coalescing disabled.

Bug 3881919

Change-Id: Ie7e6616d48f84547ce3380bfa395910b7995c05b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857141
(cherry picked from commit b2c8827c65)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859538
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-07 22:46:44 -08:00
V M S Seeta Rama Raju Mudundi
ab46ee3335 Revert "gpu:nvgpu: Expose physical gpc,tpc layout for ecc sysfs nodes." 
This reverts commit 2cc098eae7.

Reason for revert: intermittent boot failures on drv-orin-f1 and 
frspr-f1 on both AV+L and AV+Q.

Bug 3998230

Change-Id: I230ba7ba469fde3f470dab7538cc757c99360d99
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863208
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-25 11:16:12 -08:00
Kishan
2cc098eae7 gpu:nvgpu: Expose physical gpc,tpc layout for ecc sysfs nodes. 
Added new gr_config member to hold TPC physical id map.
Updated ecc stats structures to hold physical gpc,tpc
numbers. Previously logical id's were exposed via ecc
sysfs nodes.
Consumers of ecc sysfs nodes refer tpc_fs_mask which is
physical gpc/tpc layout whereas ecc sysfs nodes were updated
with logical gpc/tpc layout. This change ensures that both
use the same framework.

JIRA NVGPU-9607
Bug 3950378

Change-Id: Iac99951fc3aa9dde02e833109f32aa5bb37ea15f
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2855032
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-22 00:42:23 -08:00
Rajesh Devaraj
b754a2f0cf gpu: nvgpu: add and update falcon_dump_stats 
Add dump_falcon_info to avoid the duplication of entire
falcon_dump_stats function for new chips.

JIRA NVGPU-9216

Change-Id: I0a0c7b4655c625222a8fd3538d9e855568616e3a
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2858843
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-18 14:07:09 -08:00
Rajesh Devaraj
4bbc766454 gpu: nvgpu: add intr_0_pbcrc_pending gops for pbdma 
Add intr_0_pbcrc_pending hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: Ia08ce7761ac5b9a1af1166efbc1ecba97b54fc87
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857919
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-17 07:31:23 -08:00
Rajesh Devaraj
5aae7df6cd gpu: nvgpu: add reset_method pbdma gops 
Add reset_method hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: Ice9c3f6aea33a8dadae5841f1a6387303495ba98
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854547
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-17 07:26:24 -08:00
Rajesh Devaraj
2e73de831f gpu: nvgpu: add is_sw_method_subch pbdma gops 
Add is_sw_method_subch hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: If18a2d510f77e269cb00dde609ec1c5941622858
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2855046
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-13 05:40:54 -08:00
Rajesh Devaraj
73679f1ec8 gpu: nvgpu: update enable_fifo_interrupts 
To reuse enable_fifo_interrupts API in future chips, this patch renames
it as ga10b_fifo_enable_intr and adds it to FIFO specific header file.

JIRA NVGPU-9325

Change-Id: I9f313e417281d5861f568bd41593c5135d9c77a9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2848816
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-31 04:19:57 -08:00
Rajesh Devaraj
77841cc9bb gpu: nvgpu: update pbdma_acquire intr handling 
To reduce duplication of pbdma_handle_intr_0_legacy to new chips, this
patch makes handle_intr_0_acquire as a HAL.

JIRA NVGPU-9325

Change-Id: I225318d45078367d09fc114202d9aeb0f1be374b
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2844872
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-24 03:38:01 -08:00