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Author SHA1 Message Date
Konsta Hölttä
9d7bf6c902 gpu: nvgpu: make os fence impl headers GPL 
The Android and dmabuf os fence implementations are Linux-specific.
Change the copyright banner of the matching header files to be GPLv2 as
it should have been; they're used only in Linux code.

Jira NVGPU-5353

Change-Id: Ifd365672ba5c797de82e18a2d0e7bf69459451be
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2342000
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Peter Daifuku
f0f126d7cc gpu: nvgpu: posix: fix GPL dependencies in bitmap 
Fix up GPL issues in posix version of bitops.

Bug 2919200

Change-Id: I57fdb035b811f47e119cca2278431d3701717d89
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340983
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
681077d578 gpu: nvgpu: volta+: convert SM broadcast to SM unicast 
Starting volta, multiple SMs are supported. Ctxsw regops
require SM broadcast registers to be converted to unicast registers.

Bug 2960720
JIRA NVGPU-5502

Change-Id: Id6e87fcc993587317bcd9b6958233e39d6b41fa7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340921
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 2020-12-15 14:13:28 -06:00
Seema Khowala
98886cd28e gpu: nvgpu: volta+: add litter value for SM UNIQUE_BASE & SHARED_BASE 
Starting volta, multiple SMs are supported. In order to convert
SM broadcast registers to unicast registers, sm_unique_base
and sm_shared_base are required.

Bug 2960720
JIRA NVGPU-5502

Change-Id: Ie9ebc0ab814cf551801f6cac1298a791d184f894
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340792
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
a039261724 gpu: nvgpu: add gr.process_context_buffer_priv_segment gops 
1. Add below gr gops to process context buffer's priv segment.
int (*process_context_buffer_priv_segment)(struct gk20a *g,
					 enum ctxsw_addr_type addr_type,
					 u32 pri_addr,
					 u32 gpc_num, u32 num_tpcs,
					 u32 num_ppcs, u32 ppc_mask,
					 u32 *priv_offset);
Update all chips to use gr_gk20a_process_context_buffer_priv_segment()
as new gr hal.
2. Add and use ppc, tpc and etpc count functions to retrieve total count.

Bug 2960720
JIRA NVGPU-5502

Change-Id: I6cec36c323ff49ded853cd5cbfd9e0a28602b8ed
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340372
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Tested-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
a629b48013 gpu: nvgpu: split channel sema wakeup function 
Extract the functionality to post semaphore signals to one channel into
a separate function for readability.

Jira NVGPU-5491

Change-Id: Ib5e8d34f42a64c253b3b3b8cb9e2c5dd2656fd1f
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340466
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
23d6b36101 gpu: nvgpu: add dma_fence semaphore support 
Support exporting and importing semaphore-based synchronization with the
stable dma-fence API. The "Android" sync fence API used until now is
deprecated.

The Android sync framework is still kept as the default.

Jira NVGPU-5353

Change-Id: I9e57947adeb4d2ef5d59135ed7d008553c44f97c
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336119
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 2020-12-15 14:13:28 -06:00
Bitan Biswas
7d6645d7af gpu: nvgpu: fuse and chip revision updates for k5.4 
1. use fuse.h instead of chip-id.h in k5.4.
2. chip revision checks for TEGRA210_REVISION_A04p and
   TEGRA194_REVISION_A01 are replaced with chip id
   check and revision check for TEGRA_REVISION_A04p
   and TEGRA_REVISION_A01.

Bug 200591811
Bug 200602747

Change-Id: I3383b691e400265723214e81ac193fd1cc1946e3
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2338262
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
3bd0430aa8 gpu: nvgpu: for nvgpu-next do not reset grce engines twice 
NVGPU_ENGINE_GRCE engines are getting reset twice, once in
nvgpu_init_prepare_hw() and other time in nvgpu_ce_init_support().

To avoid this, remove NVGPU_ENGINE_GRCE engines reset from
nvgpu_init_prepare_hw.

JIRA NVGPU-5288

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Ic03dbff0a74e973ba423abfa004e49bdd8e451f7
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336450
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d44ed9d3a8 gpu: nvgpu: rollback gpfifo on error 
Submitting new work may fail in the middle of writing the gpfifo
entries. Undo the increments on the gp_put shadow pointer in case of
error to avoid submitting wrong data during the next submit.

Jira NVGPU-5491

Change-Id: I064eaac8773b24da0a56db79ac6bfd07c008da03
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340464
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
f388b1f596 gpu: nvgpu: simplify cmdbuf construction in submit 
Split out the wait cmd and incr cmd setup work in submit path to
separate functions to minimize cyclomatic complexity and to increase
readability.

Jira NVGPU-5491

Change-Id: I7dfabd2de287ae10aaae9fb8d4d85d752db8631c
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340463
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Dinesh
b79bee9cea gpu: nvgpu: CCM reduction for vidmem clear 
This is added to make a common function  nvgpu_vidmem_clear_fence_wait
that can be used by multiple callers. This helps to reduce CCM and
code duplication in vidmem unit.

JIRA NVGPU-990

Change-Id: I3a7090588abda68900849443f6a8fa1bfa246bf4
Signed-off-by: Dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332691
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 2020-12-15 14:13:28 -06:00
Shashank Singh
701c0efa8d gpu: nvgpu: enable syncpoint shim when nvlink is disabled 
Create an iova for syncpoint shim region in case iommu is enabled and
nvlink is disabled. This iova is then used to created nvgpu mem with
nvgpu_mem_create_from_phys. Which is then used to create gpu mappings.
Instead of creating another variable g->syncpt_mem's priv is used to
store the sgt which needs to be freed on deinit.

Jira NVGPU-5376

Change-Id: I0b5a8320fbbb68031912ae88cfe8c2c3804fb813
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332643
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
3875c0825f gpu: nvgpu: avoid sema/channel dependencies 
Move the per-channel hw semaphore object to be owned by the channel sync
(just like with syncpoints, too). Store just the channel ID in the hw
sema for debug prints to get rid of sema->channel dependencies. Make
nvgpu_semaphore_alloc() take a hw sema instead of a channel.

Fix up some channel-related documentation that has been incorrect.

Jira NVGPU-5353

Change-Id: I04d49da3aac50a4cea32e7393f48e6f85a80ca0d
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339931
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 2020-12-15 14:13:28 -06:00
Abdul Salam
97de1ba74d gpu: nvgpu: Use unified struct to store slave freq 
Instead of using multiple struct use a single nvgpu_clk_slave_freq
to store the slave freq of gpcclk.
With this patch single struct can be used by both clk_arb and clk_domain.
This will remove nvgpu_set_fll_clk struct as nvgpu_clk_slave_freq serves
the purpose.

NVGPU-4692

Change-Id: Ie45d63e4376b83e153a9aa75e2c4631c6dad857b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339213
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 2020-12-15 14:13:28 -06:00
rmylavarapu
700bd83b41 gpu: nvgpu: Rename/clean boardobj unit 
-Removed unwanded boardobj includes
-Renamed functions as struct as per usage

NVGPU-4484

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: I792a4b64075d5e87f911c1073717dbe7107227a1
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335991
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
8e545ef04b gpu: nvgpu: Fix boardobj allocation size 
In current implementation we are allocating boardobj
in nvgpu_boardobj_construct_super for all units and assigning
that pointer to boardobj type, as the size differe for different
units assigning the boardobj pointer to a common type will
give violations. Fixing them by allocating mem a head
and later call construct_super for elements initialization.

NVGPU-4484

Change-Id: I9b5ed1a6d8418fec48a29eee38d55fc7d83fcfab
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335989
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 2020-12-15 14:13:28 -06:00
rmylavarapu
0115c26f1b gpu: nvgpu: Boardobj lite unit refactor 
As boardobj unit is used only in PMU, the plan is to move
all the boardobj related functions/structures and Macros
to boardobj specific folders. This will remove unnecessary
usage of boardobj outside PMU.

NVGPU-4484

Change-Id: I9f0fda32e6affd1fce218eb0ac638a9dfc8b99c3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335986
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 2020-12-15 14:13:28 -06:00
Alex Waterman
5f0fdf085c nvgpu: unit: Add new mock register framework 
Many tests used various incarnations of the mock register framework.
This was based on a dump of gv11b registers. Tests that greatly
benefitted from having generally sane register values all rely
heavily on this framework.

However, every test essentially did their own thing. This was not
efficient and has caused a some issues in cleaning up the device and
host code.

Therefore introduce a much leaner and simplified register framework.
All unit tests now automatically get a good subset of the gv11b
registers auto-populated. As part of this also populate the HAL with
a nvgpu_detect_chip() call. Many tests can now _probably_ have all
their HAL init (except dummy HAL stuff) deleted. But this does
require a few fixups here and there to set HALs to NULL where tests
expect HALs to be NULL by default.

Where necessary HALs are cleared with a memset to prevent unwanted
code from executing.

Overall, this imposes a far smaller burden on tests to initialize
their environments.

Something to consider for the future, though, is how to handle
supporting multiple chips in the unit test world.

JIRA NVGPU-5422

Change-Id: Icf1a63f728e9c5671ee0fdb726c235ffbd2843e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335334
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
b8f398f6a7 gpu: nvgpu: clean up struct priv_cmd_entry 
The valid flag is no longer useful as the lifetime of priv cmd entries
is clearer than before. Delete it. Delete also the stored gva that can
be calculated from the nvgpu_mem plus offset.

Jira NVGPU-4548

Change-Id: Ibf322acbb2ab1a454e9b644af24c02d291b75633
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
(cherry picked partially from commit
b9f6512e803873aaa92218dcbc090ff31a4f9c50)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332509
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
198be2178a gpu: nvgpu: YAML changes for nvgpu-next 
Currently, nvgpu build is not syncing nvgpu-next arch and source files.
1. Add nvgpu-next yaml files to nvgpu.yaml.
2. Pass nvgpu-next source and include path to arch.py.

JIRA NVGPU-5007

Change-Id: I2ad04b0ef813912566a3b73dae39cf0373092913
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2293860
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
d03883d09d gpu: nvgpu: do not use nvgpu_writel_check in gm20b_flush_ltc 
Replace nvgpu_wriel_check with nvgpu_writel to issue clean
and invalidate in gm20b_flush_ltc.

JIRA NVGPU-5490

Change-Id: I6e1e73136e93ff06396894e5ba855f30bc3403b0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339424
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
ee216bc941 gpu: nvgpu: add NVGPU_SUPPORT_COMPRESSION flag 
Add NVGPU_SUPPORT_COMPRESSION to indicate if compression feature is
supported in nvgpu. If not, set cbc.init, cbc.ctrl and
cbc.alloc_comptags hals to NULL.
Add corresponding GPU characteristics flag and IOCTL mapping to sync
compression support status with nvrm_gpu.

JIRA NVGPU-4666

Change-Id: I2e685688ddac592b3bb918ee70c82ea5524d695a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2338926
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 2020-12-15 14:13:28 -06:00
Seema Khowala
cfc5bac059 gpu: nvgpu: add assert in nvgpu_writel_check 
nvgpu_writel_check outputs dbg message if updated read value
does not match with requested write value. Change dbg message to
error message.
Use BUG_ON for write mismatch as failure to update h/w register
is a bug and tells s/w to either add fixed delay or use timeout
to check for updated register value.

JIRA NVGPU-5490

Change-Id: Ib11b7862d2990a56259d2f8c10d75c12c84bae5d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2338004
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
e5b23f33b9 gpu: nvgpu: add internal CONFIG_SYNC wrapper 
The sync file support in Linux has been stabilized and the new config is
called CONFIG_SYNC_FILE. Even if maybe not so intended, both the
stabilized version and the legacy CONFIG_SYNC can coexist; to begin with
supporting the stabilized version, add CONFIG_NVGPU_SYNCFD_ANDROID and
CONFIG_NVGPU_SYNCFD_NONE as choice configs of which one will be set. A
later patch will extend this with a choice for CONFIG_SYNC_FILE.

Jira NVGPU-5353

Change-Id: I67582b68d700b16c46e1cd090f1b938067a364e3
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336118
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
068e00749b gpu: nvgpu: update config_userd_writeback_enable 
Field value of pbdma_config_userd_writeback_enable is changing from
0x1 to 0x0 for nvgpu-next. So,
- Update config_userd_writeback_enable() hal to accept u32 value.
- Update config_userd_writeback_enable() hal to return modified
  value after setting pbdma_config_userd_writeback_enable field.

Jira NVGPU-5162

Change-Id: I94efa20c34bb867f185778c973bd52b86902b32c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Nicolas Benech
4267008096 gpu: nvgpu: debug: remove unused dentry pointers 
Starting with kernel 5.7-rc3, the debugfs_create_u32 function returns
void instead of (struct dentry *). The rationale was that the
returned value was never used, and indeed it was not used within
NVGPU.

JIRA HK123-39

Change-Id: Ic8c2aaf9c84bcf016ed7a0183d84da311e4027d0
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2337859
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
cd7194cbc0 gpu: nvgpu: modify gmmu page table entry functions 
Move below chip agnostic gmmu pte functions to common/mm/gmmu/pte.c.
- gmmu_aperture_mask()
- pte_dbg_print()

Default big page size for all chips is 64K. So, move
gp10b_mm_get_default_big_page_size() to common file and rename as
nvgpu_gmmu_default_big_page_size().

Modify gv11b_gpu_phys_addr() to use get_iommu_bit() hal.

JIRA NVGPU-4666

Change-Id: I512c42723faf2d03e5b367879c9c385dcf52cdc2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
05df07945a gpu: nvgpu: avoid channel dependency in priv cmdbuf 
The priv cmdbuf queue needs only the vm_gk20a of the channel that owns
it. Pass the vm to the queue constructor and have the channel code store
the queue to itself instead of poking at the channel from the queue
code. Adjust the cmdbuf queue api to take the queue, not the channel.

Move the inflight job fallback calculation to the channel code. The size
of the channel gpfifo isn't needed in the queue; just the job count is.

[not part of the cherry-pick: a bunch of MISRA mitigations.]

Jira NVGPU-4548

Change-Id: I4277dc67bb50380cb157f3aa3c5d57b162a8f0ba
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329659
(cherry picked from commit 83b2276f7bea563602eee20ce24b70ce70c8475a)
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
991002c88b gpu: nvgpu: hide struct priv_cmd_entry 
The type for entries allocated from the priv cmd queue is no longer
necessary to be visible for its users other than as an opaque handle,
except for a few minor debug prints. Make those prints output the entry
pointer value instead and move the struct definition to priv_cmdbuf.c.

Jira NVGPU-4548

Change-Id: Ia75ff41d840ac928561525a46d5973640e4b5f7e
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329658
(cherry picked from commit 3292cdadbc78ca129d1e0878c3947b0839487fc2)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332507
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
b436877190 gpu: nvgpu: replace nvgpu_log with nvgpu_err for CE stall interrupts 
Replace nvgpu_log with nvgpu_err for ce stall interrupt messages.

Jira: NVGPU-5034

Change-Id: I794461431ec6fadc322fe05a4f53f619c5370052
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335702
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 2020-12-15 14:13:28 -06:00
Abdul Salam
076c85f813 gpu: nvgpu: Move clk_pmu struct from public include to unit include 
As a part of refactoring move nvgpu_clk_pmupstate from public to
private include.
Also remove all function pointers from the struct and use functions
as only single pstate is supported.
This function pointers were created to address multiple pstate support
which no more needed now.

NVGPU-4690

Change-Id: Iee556feed4a25902faba87a606418861185e4089
Signed-off-by: Abdul Salam <absalam@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
6974f784e2 gpu: nvgpu: Update cbc_init_support() return error 
Currently, nvgpu_cbc_init_support() doesn't return error if
cbc.alloc_comptags() fails. Modify nvgpu_cbc_init_support() to check
error returned by cbc.alloc_comptags(). If alloc_comptags() fails, free
allocated cbc memory and set cbc pointer to NULL.

JIRA NVGPU-4666

Change-Id: Id7edaeebc81e7d7029d98bcdbffaf6506c8f0979
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
0610a0b2d3 gpu: nvgpu: nvgpu_mem: Makefile for dgpu 
Add Makefile to compile nvgpu_mem module tests for dGPU.

Jira NVPGU-5217

Change-Id: I938b5a2faaee20aaa0ea4b60e17310dc2eb364b9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333500
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
4f682bf107 gpu: nvgpu: igpu and dgpu driver libs 
Different build flags are used for iGPU and dGPU in
safety build. In order to support dGPU in unit tests,
a separate library is needed for the driver.

Added makefiles to build:
- libnvgpu-drv-igpu.so
- libnvgpu-drv-dpgu.so

Updated scripts and units makefiles to use libnvgpu-drv-igu
by default.

Jira NVGPU-5217

Change-Id: Ibcc56088723cec5cb2d0ac42725102ae0c886014
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333499
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
80285be2da gpu: nvgpu: unit: add --driver-load-path arg 
Add --driver-load-path option to specify which library to
load for driver.
There is already an --unit-load-path option that can be
used to specify where to load units from.

Example usage:
./nvgpu_unit --nvtest --unit-load-path units/dgpu \
      --no-color --num-threads 1 \
      --driver-load-path ./libnvgpu-drv-dgpu.so

Jira NVGPU-5217

Change-Id: I6af5d2029138b25a6715154779b812d30052e9e9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333498
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 2020-12-15 14:13:28 -06:00
Abdul Salam
88d3640bc5 gpu: nvgpu: Refacotor clk_domain Unit 
As a part of refactoring this patch does the following
*Move local struct to unit specific header file
*Move nvgpu_pmu_clk_domain_freq_to_volt from clk.c to
clk_domain.c
*Move PMU specific struct to ucode_clk_inf.h
*Merge content from nvgpu/clk.h to pmu/clk/clk.h
*Update yaml file
This will help to have arch consistency across all units.

Change-Id: Ied5c6ee637e7fd5bbdee3f5bc3f6cf216454428a
Signed-off-by: Abdul Salam <absalam@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
f0896f94e1 gpu: nvgpu: Add falcon gops 
Add falcon gops for accessing below constants. This is
required for nvgpu-next.

falcon_falcon_dmemc_blk_m
falcon_falcon_imemc_blk_f

JIRA NVGPU-4834

Change-Id: I1a60f473470a7a03fb31dceecfccd91fcc690de9
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
c060e754fc gpu: nvgpu: ELPG dump stats at shutdown 
ELPG_DISALLOW command fails during gk20a shutdown.
It was due to nvgpu_can_busy() which was returning
0 before without acknowledging the ELPG_DISALLOW
command.

Since the system is shutting down so fix this issue
by setting the ACK for disallow command without
waiting for actual ACK from PMU.
In doing so the state machine is also maintained
properly and the driver does not dump fail stats.

BUG 200588696

Change-Id: I943d8e6108fa0f9c418ccb1a7f061307823f1ec6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
9bee2fe660 gpu: nvgpu: prealloc priv cmdbuf metadata 
Move preallocation of priv cmdbuf metadata structs to the priv cmdbuf
level and do it always, not only on deterministic channels. This makes
job tracking simpler and loosens dependencies from jobs to cmdbuf
internals. The underlying dma memory for the cmdbuf data has always been
preallocated.

Rename the priv cmdbuf functions to have a consistent prefix.

Refactor the channel sync wait and incr ops to free any priv cmdbufs
they allocate. They have been depending on the caller to free their
resources even on error conditions, requiring the caller to know how
they work.

The error paths that could occur after a priv cmdbuf has been allocated
have likely been wrong for a long time. Usually the cmdbuf queue allows
allocating only from one end and freeing from only the other end, as
that's natural with the hardware job queue. However, in error conditions
the just recently allocated entries need to be put back. Improve the
interface for this.

[not part of the cherry-pick:] Delete the error prints about not enough
priv cmd buffer space. That is not an error. When obeying the
user-provided job sizes more strictly, momentarily running out of job
tracking resources is possible when the job cleanup thread does not
catch up quickly enough. In such a case the number of inflight jobs on
the hardware could be less than the maximum, but the inflight job count
that nvgpu sees via the consumed resources could reach the maximum.
Also remove the wrong translation to -EINVAL from err from one call to
nvgpu_priv_cmdbuf_alloc() - the -EAGAIN from the failed allocation is
important.

[not part of the cherry-pick: a bunch of MISRA mitigations.]

Jira NVGPU-4548

Change-Id: I09d02bd44d50a5451500d09605f906d74009a8a4
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329657
(cherry picked from commit 25412412f31436688c6b45684886f7552075da83)
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
bc4f74d854 gpu: nvgpu: add pg209 sku device id 
Jira NVGPU-5375

Change-Id: I745832b3bd1865abaca24b4b96fd174097542427
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333424
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
85b9c98eba gpu: nvgpu: init hal for nvgpu-next dgpu 
Add hooks for nvgpu-next dgpu init hal.

Jira NVGPU-5382

Change-Id: I5395a32ceda21b43b186756ba6dd5937251c3548
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
68caee196a gpu: nvgpu: add mm.mmu_fault.parse_mmu_fault_info gops 
Add mm.mmu_fault.parse_mmu_fault_info gops. This is required
for nvgpu-next.
Also add mmu_engine_id type in mmu_fault structure. This variable
will be set in parse_mmu_fault_info hal so that
gv11b_mm_mmu_fault_handle_other_fault_notify does not depend
upon any chip specific h/w header. This is needed because
BAR2 mmu engine id has changed in nvgpu-next.

JIRA NVGPU-5032

Change-Id: I0c5e9ef607aff5b105f59582013cbfb31396290a
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
91401cc849 gpu: nvgpu: build flag for dGPU in safety 
CONFIG_NVGPU_DGPU already exists to enable dGPU support.
Replace NVGPU_FORCE_DGPU_SAFETY_PROFILE with CONFIG_NVGPU_DGPU.

Jira NVGPU-5277

Change-Id: Ia1617a42269b18c1a443d91f9ca2ba38afd4a6f9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2322899
(cherry picked from commit 9882b44709ef472b9113e3cd43974fe177eeeb24)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328532
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
6fc1e41150 gpu: nvgpu: split submit on deterministic 
Avoid repetitive branching on the c->deterministic flag and on build
time flags by breaking the submit function on the runtime flag into two
functions of which one gets called.

In deterministic mode the job tracking conditions are simpler, there are
a few extra prechecks to guarantee deterministic latency and the
railgate corner case, and deferred cleanup is never done.

In nondeterministic mode job tracking has more conditions, a power
reference is taken for the job lifetime, and deferred cleanup is
assumed.

These two paths still share some common code. Split it to two more
functions to act as easy building blocks so that the main logic is
apparent.

Jira NVGPU-4548

Change-Id: I64f91dcf09acb16f409dc04a12ad1e144d0cce56
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333728
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
b077c6787d gpu: nvgpu: split sync and gpfifo work in submit 
Make the big submit function somewhat shorter by splitting out the work
to do job allocation, sync command buffer creation and gpfifo writing
out to another function. To emphasize the difference between tracked and
fast submits, add two separate functions for those two cases.

Jira NVGPU-4548

Change-Id: I97432a3d70dd408dc5d7c520f2eb5aa9c76d5e41
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
96bea78d55 gpu: nvgpu: add init_hw, intr_enable hals to ce gops 
Add following two HALs to ce gops:
- init_hw:
  Build a list of non-stall interrupt vectors and register them
  with struct nvgpu_mc.
- intr_enable:
  Enable ce engine stall, non-stall interrupts.

Jira: NVGPU-5034

Change-Id: Ibdc768c2bce778237233803ebbbd5190362b4578
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329166
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 2020-12-15 14:13:28 -06:00
ajesh
1500ce829a gpu: nvgpu: assert for OS API errors in non fusa 
Handle the OS API errors with assert in non FUSA builds also.

Jira NVGPU-4987

Change-Id: I90428e845ae9f934b0d4bce08ab93f13f3fde2f8
Signed-off-by: ajesh <akv@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Abdul Salam
af3311ddea gpu: nvgpu: Refactor clock_domain unit 
As a part of refactoring move nvgpu_clk_domain struct from public
to private.
This will help to have arch consistency across all units.
Use public functions to fetch the data across other units.
The following functions are added to access data in clk_domain unit.
*nvgpu_pmu_clk_domain_get_f_points()--> To get freq points
*nvgpu_pmu_clk_domain_update_clk_info() --> To update change seq script
with clock domain data

NVGPU-4689

Change-Id: Idc85e3cf5bbe1b80766ce6c9f07b3305ef04cbdc
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332185
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 2020-12-15 14:13:28 -06:00
Seema Khowala
aff5497907 gpu: nvgpu: add intr_unit_bitmask i/p param for fb.intr.isr 
tu104 onwards, fb interrupt status/enable/disable moved from
fb_niso_intr_* reg to fb_*vector* registers.
At the top level, fb interrupt status/enable/disable is done
using hub_intr bit in mc_intr registers.

Starting nvgpu-next, this has changed.

JIRA NVGPU-5032

Change-Id: Ib54170b055b83e2696312c811c2e3ba678749359
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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