Currently for every +/-5 degC change in
temperature, PMU internally evaluate VF curve on
temp change and will send VFE callback to NVGPU for
initiating change seq to program voltage and frequency.
This is the only callback we receive on temp change
which we handle in perf unit, and we don't have any
other temp events raised by PMU.
So, deleting the therm event handler.
NVGPU-4360
Change-Id: I3c7279dcf691135c178b6a05766403a935bc7e73
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2241488
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Add support in nvgpu to parse and get the freq cap from DT.
The patch does below
Parse the DT and gets the freq cap value during probe.
During clk_arb init compare this with P0.Max and takes the lowest.
Send change_seq with the new value and set dgpu freq.
Use the lowest for "get points","get default","set VF".
Bug 200556366
Change-Id: Ie10243f9bf83cb5ae07ebcc4cdc8efaffa56c309
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204644
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Move graphics related defs and functions under CONFIG_NVGPU_GRAPHICS
switch.
Move classes not supported in GV11B under CONFIG_NVGPU_NON_FUSA
switch.
Add missing valid class numbers to gpu_class.is_valid HAL.
Also remove un-used class defs from class.h header.
Lot of qnx safety tests are still using graphics 3d class.
Until those tests got fixed, allowing 3d graphics class
as valid class for safety build.
JIRA NVGPU-4301
Change-Id: Ifd2a13bee3210821799c2bca10e7245eb3c79121
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224658
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Whitelist 2 MISRA Rule 17.2 violations in MM that were approved as
deviations in TID-278. These two violations are for recursive functions
that handle page table descriptors in the GMMU page table. Both cases
are tightly controlled recursion by limiting the recursion depth to the
number of possible page table levels in the hardware. For current
hardware that is a maximum recursion depth of 5 which is easily an
acceptable depth and should cause no stack issues.
JIRA NVGPU-3489
JIRA NVGPU-3492
JIRA TID-278
Change-Id: I5b801ff77f66bb8698f1d6adcd41ebbad3f86f92
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2230077
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This function gets the GPU chip architecture, implementation and
revision information by reading the MC boot register, hence it
is more suited to be located in HAL files.
test_check_gpu_state is now being run after test_hal_init as the
gops.mc needs to be initialized for test_check_gpu_state subtest.
JIRA NVGPU-2524
Change-Id: I85355af11d3505a9eb4f10a3fe4e6d9b56285047
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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gk20a.h will include gops_mc.h to contain the mc ops definitions. Add
doxygen comments for the HAL functions that are called directly.
Also move mc_gp10b_intr_pmu_unit_config to non-fusa HAL file.
JIRA NVGPU-2524
Change-Id: I4f326332d7842211b004b372d79fac9fe6ed40e7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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The two MM functions nvgpu_set_pd_level() and nvgpu_vm_do_free_entries()
are simple recursive functions for processing page descriptors (PDs) by
traversing the levels in the PDs. MISRA Rule 17.2 prohibits functions
calling themselves because "unless recursion is tightly controlled, it
is not possible to determine before execution what the worst-case stack
usage could be." So, this change limits the recursion depth of each of
these functions to the maximum number of page table levels by checking
the level against the MM HAL max_page_table_levels().
This also required configuring this HAL in various unit tests as they
were no previously using this HAL.
JIRA NVGPU-3489
Change-Id: Iadee3fa5ba9f45cd643ac6c202e9296d75d51880
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
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nvgpu_falcon_setup_bootstrap_config functionality can be kept static.
nvgpu_falcon_bl_bootstrap and nvgpu_falcon_bl_info are removed as it
is replaced by nvgpu_falcon_hs_ucode_load_bootstrap.
Update the test case accordingly, SWUTS and doxygen comments. Other
nits addressed about doxygen documentation.
JIRA NVGPU-2412
Change-Id: Idaa670ce6d6d6b735b4a2af34e1f1a229ff2a3e9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2220089
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Add doxygen comments to all the FUSA public APIs and HALS
The APIs identified as NON-FUSA are -
a. nvgpu_fbp_get_num_fbps()
b. nvgpu_fbp_get_rop_l2_en_mask()
Add @cond ... @endcond to skip NON FUSA functions from
design document.
The FBP HAL fbp.fbp_init_support() is redundant and will be replaced
by calls to nvgpu_fbp_init_support() directly.
JIRA NVGPU-4140
Change-Id: I08ec79dfcab7b898b40491997963466938e5e4cd
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2221967
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Sometimes nvgpu_sw_quiesce_thread does not get a
chance to run before common.init unit tests complete.
When it finally gets scheduled, related gk20a
context is invalid and it crashes in the pthread
wrapper.
Make sure nvgpu_sw_quiesce_thread has started in
nvgpu_sw_quiesce_init_support, to avoid such issues.
Bug 2732985
Change-Id: I0a46f271a926b5f0c203b465f69556b2b46d96c5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2222560
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When reviewing some VM mapping code I found the name of the function
that actually maps the passed buffer to be confusing. It was:
nvgpu_vm_map_compression_comptags()
This function does actually do the map and work out some comptags
related stuff. But I think this would be easier to read in the code
as:
nvgpu_vm_do_map()
As this is much more literally what the function is actually doing.
Change-Id: I9a945b198887f5fb23b8be622c8411f97358dbed
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2220339
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Functions for copying to falcon memory typecast from pointer to char of
input buffer to pointer to u32 since falcon data registers are written
in 4-bytes. Firmware data is generally byte stream and hence we won't
be able to deal with input buffer as pointer to u32.
Hence, misra rule 11.3 deviation is required for these casts. Firmware
data is also not aligned at word boundary sometimes hence we need to
copy it to aligned buffer to conform to the deviation recommendation.
hal/falcon/falcon_gk20a_fusa.c:136
Checker: MISRA C-2012 Rule 11.3 (Required)
misra_c_2012_rule_11_3_violation: The object pointer expression "src"
of type "u8 *" is cast to type "u32 *".
This patch implements copy to falcon memory from unaligned source byte
by byte and casts the input buffer to u32 pointer otherwise.
JIRA NVGPU-4128
Change-Id: Iff3cc1010b8e209ec453c10c6d46953cf5a8adbe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210321
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In the change_seq of latest ucode, the boot pstate
index was taken from pstate board_objs instead of the
value from change_input. This forces the need of
introducing boot index in pstate board_obj structure.
The index is the performance table entry index of
P0 pstate.
The ucode change is described in P4CL #27304645
NVGPU-4081
Change-Id: Id3f4a1da7015cd6b7efe555529f1fa13c9f3b391
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202363
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Currently nvgpu reads the temperature by reading the
NV_THERM_I2CS_SENSOR_00 register. Below are the issues
with current approach
1) NV_THERM_I2CS_SENSOR_00 doesn't support
fractional precision which is POR.
2) It doesn't support negative temperatures which
is required for Auto.
3) It doesn't take into account the right POR
sensor in VFE VBIOS tables.
From therm channel get status interface we can read the
current temperature from PMU.
NVBUG - 200549047
Change-Id: I2fb21926208876f3d3bebe3f2dee08edafedbc7d
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196224
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There are 2 instances where some code is unreachable in vm.c
- The nvgpu_insert_mapped_buf function always returned 0, so any
associated error handling was unreachable. This patch changes
the function to return void instead.
- A cleanup section to unmap a buffer in case of error was also
unreachable.
JIRA NVGPU-909
Change-Id: I6d8343b2994d314992a61dd640b10e68fbbc5e1e
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217677
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Update struct nvgpu_fecs_ecc_status comments for doxygen.
Move structures for method, mailbox and cond outside
the nvgpu_fecs_method_op struct, for better doxygen
format. Defining sturct within struct doesnot look
good in doxygen.
Jira NVGPU-4107
Change-Id: I34b2249119e5578c568139f958e6edab9d75d7c8
Signed-off-by: Vinod G <vinodg@nvidia.com>
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-Renamed ACR structs for FUSA, ACR FUSA code has struct names
ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to acr_blob_construct.c/h
JIRA NVGPU-2516
Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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Add NVGPU_INIT_TABLE_ENTRY for nvgpu_sw_quiesce_init_support.
Add g->sw_quiesce_init_done to avoid multiple initializations,
and check if deinit is needed in nvgpu_sw_quiesce_remove_support.
This avoids issues in common.init unit tests.
Jira NVGPU-4089
Change-Id: Ife3aa43d5f1f86899a895e4576e38ecc28a8e371
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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For MMU and PBDMA faults, error notifier needs to be set
before entering SW quiesce. Otherwise it ends up with
default NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT.
Added nvgpu_rc_mmu_fault to:
- call g->ops.fifo.recover when recovery is enabled
- set MMU error when recovery is disabled
Updated nvgpu_rc_pbdma_fault to set PBDMA error when
recovery is disabled as well.
Wait for deferred interrupts to complete before actually
entering SW quiesce state, to make sure error notifier has
been set.
Jira NVGPU-4127
Change-Id: Ia84c723e021e397391c6c609d4bb96c06afdcc47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210909
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nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc
APIs. So, move the enum into mc.h, and replace the include of unit.h
with mc.h where appropriate. And update the yaml arch.
JIRA NVGPU-4144
Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
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