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155 Commits

Author SHA1 Message Date
Alex Waterman
5f0fdf085c nvgpu: unit: Add new mock register framework 
Many tests used various incarnations of the mock register framework.
This was based on a dump of gv11b registers. Tests that greatly
benefitted from having generally sane register values all rely
heavily on this framework.

However, every test essentially did their own thing. This was not
efficient and has caused a some issues in cleaning up the device and
host code.

Therefore introduce a much leaner and simplified register framework.
All unit tests now automatically get a good subset of the gv11b
registers auto-populated. As part of this also populate the HAL with
a nvgpu_detect_chip() call. Many tests can now _probably_ have all
their HAL init (except dummy HAL stuff) deleted. But this does
require a few fixups here and there to set HALs to NULL where tests
expect HALs to be NULL by default.

Where necessary HALs are cleared with a memset to prevent unwanted
code from executing.

Overall, this imposes a far smaller burden on tests to initialize
their environments.

Something to consider for the future, though, is how to handle
supporting multiple chips in the unit test world.

JIRA NVGPU-5422

Change-Id: Icf1a63f728e9c5671ee0fdb726c235ffbd2843e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335334
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
068e00749b gpu: nvgpu: update config_userd_writeback_enable 
Field value of pbdma_config_userd_writeback_enable is changing from
0x1 to 0x0 for nvgpu-next. So,
- Update config_userd_writeback_enable() hal to accept u32 value.
- Update config_userd_writeback_enable() hal to return modified
  value after setting pbdma_config_userd_writeback_enable field.

Jira NVGPU-5162

Change-Id: I94efa20c34bb867f185778c973bd52b86902b32c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2330160
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 2020-12-15 14:13:28 -06:00
Prateek sethi
470fe3a6d4 gpu: nvgpu: unit: update cg unit test 
CG unit tests check for invalid registers access during configuration
of various CG modes for various units that involve multiple registers
accesses. Since ECC detect is now being done in hal init now,
corresponding registers need to be added to io space.

Bug 2919887

Change-Id: I8ded6a95952d810d9c8627a71752266e493e2c47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332262
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
76295a5aeb gpu: nvgpu: redundant dependency on driver 
Makefile.units.common.tmk already specifies dependency
on nvgpu driver interface.

Remove redundant dependency in units makefiles.

Jira NVGPU-5217

Change-Id: I94cbe707c25f41f0e61915c243fd55fd4bda9ccf
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2322205
(cherry picked from commit d9bdd8f589c121802c74da53945baa677578f71c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325907
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
c6908922e5 gpu: nvgpu: move generic preempt hals to common 
- Move fifo.preempt_runlists_for_rc and fifo.preempt_tsg hals to common
source file as nvgpu_fifo_preempt_runlists_for_rc and
nvgpu_fifo_preempt_tsg.

Jira NVGPU-4881

Change-Id: I31f7973276c075130d8a0ac684c6c99e35be6017
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323866
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
4f80c6b8a9 gpu: nvgpu: add channel_user_syncpt 
Refactor user managed syncpoints out of the channel sync infrastructure
that deals with jobs submitted via the kernel api. The user syncpt only
needs to expose the id and gpu address of the reserved syncpoint. None
of the rest (fences, priv cmdbufs) is needed for that, so it hasn't been
ideal to couple with the user-allocated syncpts.

With user syncpts now provided by channel_user_syncpt, remove the
user_managed flag from the kernel sync api.

This allows moving all the kernel submit sync code to be conditionally
compiled in only when needed, and separates the user sync functionality
in a more clear way from the rest with a minimal API.

[this is squashed with commit 5111caea601a (gpu: nvgpu: guard user
syncpt with nvhost config) from
https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325009]

Jira NVGPU-4548

Change-Id: I99259fc9cbd30bbd478ed86acffcce12768502d3
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321768
(cherry picked from commit 1095ad353f5f1cf7ca180d0701bc02a607404f5e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319629
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 2020-12-15 14:13:28 -06:00
vinodg
9d577b8d9a gpu: nvgpu: unit: remove gv11b_channel_debug_dump test 
dump_channel hal is moved to common code.
Remove the test_gv11b_channel_debug_dump

Jira NVGPU-5109

Signed-off-by: vinodg <vinodg@nvidia.com>
Change-Id: If04314c09d9f7f0c789752a8a003e012a629d9be
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323553
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 2020-12-15 14:13:28 -06:00
Terje Bergstrom
caf9ba229f gpu: nvgpu: unit: Remove invalid dereference 
test_tsg_format_gen() accessed test_args->timeslice when test_args
has not been initialized.

Change-Id: Ia72c5371c8634b7b1fe54c9aa20693edc47cb762
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318389
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 2020-12-15 14:13:28 -06:00
Terje Bergstrom
7a71aba234 gpu: nvgpu: unit: Fix header guards 
Fix cases where header guard #ifdef and #define had a mismatch.

Change-Id: I74aec2736c467f79e9786880d3e3847ee86a2466
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318388
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 2020-12-15 14:13:28 -06:00
Terje Bergstrom
3569e21518 gpu: nvgpu: unit: Several fixes for initializations 
Structs with structs inside them need to be initialized with double
braces. Also add a couple of missing initializations.

Change-Id: I0aa5f7ac008b8db4bececa92807f598f2f3081bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318387
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
46761356e5 gpu: nvgpu: make channel sync ops const 
The function pointers for the syncpoint and semaphore implementations of
struct nvgpu_channel_sync do not change in runtime. Make this more
explicit by having the pointers in predefined private structures. Each
instance of a sync (which there are one per open channel) gets a pointer
to an ops structure instead of a list of all the individual ops.

Jira NVGPU-4548

Change-Id: I361b74bdfe32470203760d11c30e048cb4d20b77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318242
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
8ec4395e82 gpu: nvgpu: build flag for deterministic channel 
Add CONFIG_NVGPU_DETERMINISTIC_CHANNELS and fix
preprocessor #ifdefs to allow compiling kernel mode
submit without deterministic feature enabled.

Jira NVGPU-4661

Change-Id: I4aa678715824e8981d39bd8db0c5ae61ef3a675c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310325
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 2020-12-15 14:13:28 -06:00
shashank singh
a987a244c2 gpu: nvgpu: add test type for boundary values checks in SWUTs 
-Allow only usermode submit, check for gpfifo max size.
-Map buffer offset must be page aligned and in multiple of page size.
-Check for unmapped address whether it's alloced or not.
-Offset in alloc space must be multiple of page size.
-Free space offset must be in the range of alloced space.

Jira NVGPU-4470

Change-Id: I9d5e4eb121d6d462f8b8d17b31c839b34d7d6c1d
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298188
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 2020-12-15 14:13:28 -06:00
shashank singh
0b4ccc7247 gpu: nvgpu: ignore deterministic submit flag for safety 
Safety only supports usermode submits so there is no need to process
DETERMINISTIC submit flag. For safety, while processing DETERMINISTIC
submit flag we are only setting deterministic field of struct
channel_gk20a and taking power reference with gk20a_busy(). On qnx
safety deterministic field is just used to check the syncpoint
allocation and taking power reference is a noop.

Jira NVGPU-4378

Change-Id: I1dc256db7d9fab93bef8fcc42bdb36f611b3ef40
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284644
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Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Nicolas Benech
acd459237a gpu: nvgpu: unit: update FIFO SWUTS for inst_block 
Adds nvgpu_inst_block_addr and nvgpu_free_inst_block to FIFO SWUTS.

JIRA NVGPU-3510

Change-Id: Ia65a53dfe7f976c271c2f7cc5da9ffa9d676aac4
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289243
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
f2446737fd gpu: nvgpu: fifo: add coverage & traceability 
This patch adds new channel and sync test to improve coverage. This
patch also updates SWUTs target tag to increase function traceability
and updates test type.

Jira NVGPU-4817

Change-Id: I52a7fa27f61e7e465d2ede25b92745413f17e50b
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280963
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
cffefda3e4 gpu: nvgpu: unit: traceability for runlist reload 
Fix 'Targets:' statement for:
- gops_runlist.reload

Jira NVGPU-4890

Change-Id: I944854c79bd8a772a4b5f3f10d342f3650fbd772
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2285807
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
75175d8081 gpu: nvgpu: unit: more traceability for fifo 
Add/fix 'Targets:' statements for:
- nvgpu_engine_status_get_ctx_id_type
- nvgpu_engine_status_get_next_ctx_id_type
- gm20b_pbdma_reset_method
- gm20b_pbdma_restartable_0_intr_descs
- gm20b_pbdma_disable_and_clear_all_intr
- gm20b_pbdma_clear_all_intr
- gm20b_pbdma_get_fc_target
- nvgpu_bug_exit
- nvgpu_bug_cb_from_node

Jira NVGPU-4890

Change-Id: I984542aa7daace85843fe6858d7c27b310046b28
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284481
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
95fc0571d7 gpu: nvgpu: unit: traceability for tsg disable 
Fix 'Targets:' statement for:
- gops_tsg.disable
- nvgpu_tsg_disable

Fix test description for:
- gv11b_tsg_enable

Jira NVGPU-4890

Change-Id: I25b4be03d59b0932f802acc41f1ee488b812ee8e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284771
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
e0a6000456 gpu: nvgpu: update SW quiesce 
Update SW quiesce as follows:
- After waking up sw_quiesce_thread, nvgpu_sw_quiesce
  masks interrupts, then disables and preempts runlists
  without lock. There could be still a concurrent thread
  that would re-enable the runlist by accident. This is
  very unlikely and would mean we are not in mission mode
  anyway.
- In sw_quiesce_thread, wait NVGPU_SW_QUIESCE_TIMEOUT_MS,
  to leave some time for interrupt handler to set error
  notifier (in case of HW error interrupt). Then disable
  and preempt runlists, and set error notifier for remaining
  channels before exiting the process.

Also modified nvgpu_can_busy to return false in case
SW quiesce is pending. This will make subsequent
devctl to fail.

Jira NVGPU-4512

Change-Id: I36dd554485f3b9b08f740f352f737ac4baa28746
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2266389
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
2fb56f2cea gpu: nvgpu: add bvec check for common.fifo input 
This patch adds boundary value check for common.fifo parameters as
listed below.
1. nvgpu_channel_setup_bind() includes a condition to check that value
of num_gpfifo_entries does not exceed 2^31. Otherwise prints message and
returns error.
2. nvgpu_tsg_bind_channel() includes a condition to check if channel
subctx had ASYNC id. If true, runqueue selector is set to 1 and 0
otherwise. This check is to be moved from devctl to common.fifo.

Jira NVGPU-4817

Change-Id: Id1c9253945859c245e584b5c42b3285a6b620055
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2278613
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
bdaa8519d5 gpu: nvgpu: unit: improve coverage for gv11b tsg HAL 
Add test for the following HAL:
- gv11b_tsg_enable

Jira NVGPU-4890

Change-Id: Ia79be676098e18ca71f6f9983485bf107c15f37c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280135
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
45a6b873d2 gpu: nvgpu: unit: traceability for fifo 
Fix 'Targets:' statements and/or add explicit tests for:
- gops_fifo.fifo_init_support
- gops_fifo.fifo_suspend
- gv11b_tsg_unbind_channel_check_eng_faulted
- nvgpu_tsg_from_ch
- nvgpu_tsg_alloc_sm_error_states_mem
- nvgpu_tsg_cleanup_sw
- nvgpu_tsg_set_error_notifier
- nvgpu_tsg_enable_sched
- nvgpu_tsg_default_timeslice_us
- nvgpu_tsg_get_from_id
- nvgpu_tsg_disable_sched
- nvgpu_tsg_release_common
- nvgpu_tsg_check_and_get_from_id
- nvgpu_tsg_open_common
- gv11b_pbdma_config_userd_writeback_enable
- gv11b_tsg_deinit_eng_method_buffers

Jira NVGPU-4890

Change-Id: I298b9f18318105cee8dc882767e30729e7106ccc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280134
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
55510f266d gpu: nvgpu: unit: improve coverage for engines 
Improve branch coverage for the following functions:
- nvgpu_engine_get_active_eng_info
- nvgpu_engine_get_ids
- nvgpu_ce_engine_interrupt_mask
- nvgpu_engine_get_gr_runlist_id

Add unit tests for the following functions:
-_nvgpu_engine_get_fast_ce_runlist_id
- nvgpu_engine_is_valid_runlist_id
- nvgpu_engine_id_to_mmu_fault_id
- nvgpu_engine_mmu_fault_id_to_engine_id
- nvgpu_engine_get_mask_on_id
- nvgpu_engine_get_id_and_type
- nvgpu_engine_find_busy_doing_ctxsw
- nvgpu_engine_get_runlist_busy_engines
- nvgpu_engine_mmu_fault_id_to_veid
- nvgpu_engine_mmu_fault_id_to_eng_id_and_veid
- nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id

Jira NVGPU-4511

Change-Id: Ib340df17468ff3447e271a86af9a47a067f6ad11
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2262222
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
50af902b71 gpu: nvgpu: unit: fifo: preempt-gv11b unit test 
This unit test covers all nvgpu.hal.fifo.preempt.gv11b module lines and
branches.

Jira NVGPU-4675

Change-Id: I5b7104c242e07fc61c4d155de3c0003b2bea7dfe
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2274044
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
652cff2cd0 gpu: nvgpu: unit: fifo: move assert to unit_assert 
unit_assert macro is provided to check a condition and execute bail_out
action given as a second argument.
Currently, in fifo unit, unit_assert() is redefined as assert with
common bail_out action. However, name assert() creates confusion with
linux assert macro. So, this patch removes redefined assert macro and
replaces with unit_assert.

Jira NVGPU-4684

Change-Id: I3a880f965a191f16efdabced5e23723e66ecaf3c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2276863
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
dfc0f3342a gpu: nvgpu: unit: complete tsg coverage 
Previous pruning rules in test_tsg_unbind_channel were
skipping the case where both tsg unbind and update runlist
fail.

Modified pruning rules to cover all cases.

Jira NVGPU-4673

Change-Id: I38a63347483252deb83fa079545cead59c7ec594
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master.nvidia.com/r/c/linux-nvgpu/+/2276011
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
2540a98aa4 gpu: nvgpu: unit: update 'Targets' for fifo units 
This patch adds a number of missing 'Targets' fields in the SWUTS of
various fifo units, fixes some missing ones and adds gops based
targets.

Jira NVGPU-4376

Change-Id: I445196e7092b01853786f40b860b29abc5d68371
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276680
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
0836f31c47 gpu: nvgpu: unit: improve gv11b tsg coverage 
test_gv11b_tsg_bind_channel_eng_method_buffers was missing
in the list of tests for the module.

Added the test, and fixed couple issues:
- wrong test on gpu_va in valid case.
- NULL pointer assignment during test setup, when
  tsg->eng_method_buffers is NULL.

Jira NVGPU-4673

Change-Id: I2478425f0380540e8295325ffd3df672dc5d9fd0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276068
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
a252ab1b0d gpu: nvgpu: unit: improve gm20b pbdma coverage 
Add the following cases:
- timeout == 0 in gm20b_pbdma_acquire_val
- 32-bit overflow in pbdma_method1_r computation.

Note: 32-bit overflow for pbdma_method0_r in
gm20b_pbdma_is_sw_method_subch is hindered by overflow
in pbdma_method1_r which occurs first.

Jira NVGPU-4673

Change-Id: If8202a4397115efb5af490b1ce974b43699e15c6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276051
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
b3960b2628 gpu: nvgpu: unit: improve gm20b channel coverage 
Add cases to trigger BUG() when passing invalid ch->chid.
This causes BUG() when computing register address for
ccsr_channel_inst_r(i) and ccsr_channel_r(i).

Jira NVGPU-4673

Change-Id: I313c6e6e65b38310af39f9817bb2398edf118d89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276022
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
4649631d38 gpu: nvgpu: unit: fix channel UT failures 
Currently, it seems that channel UT triggers segmentation fault in the
UT framework. Modify test_ch_referenceable_cleanup to confirm test
results using fifo pointer instead of channel pointer. This patch adds
error messages in some tests in case of failures.

Jira NVGPU-4817

Change-Id: I70121e5d082bae5e71cf1dab28a75a888a62ad40
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2275296
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
6828487f70 gpu: nvgpu: unit: coverage for gm20b pbdma status 
Add coverage for the following function:
- gm20b_read_pbdma_status_info

Jira NVGPU-4673

Change-Id: I30c20932f84aac4a96efcb023ca85c5fbaecac1c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2270924
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
67696c6870 gpu: nvgpu: conditionally compile tsg event ids 
event_id_list and event_id_list_locks fields are only
needed in nvgpu_tsg when CONFIG_NVGPU_CHANNEL_TSG_CONTROL
is defined.

Conditionally compile those fields and related code,
so that they are removed from safety build.

Jira NVGPU-4376

Change-Id: I8678aa1b8cd4166aa37bcb42cda1eb9c703fd32f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2273261
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
2f29272d61 gpu: nvgpu: line coverage for gk20a_runlist_wait_pending 
Use fault injection to test nvgpu_timeout_init failure case
in gk20a_runlist_wait_pending.

Jira NVGPU-4673

Change-Id: I62810db0877339909d99f1de8d14847557ecb8fd
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2272458
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
399a8f3125 gpu: nvgpu: unit: nvgpu.hal.fifo.ctxsw_timeout UT 
This unit test covers most of the nvgpu.hal.fifo.ctxsw_timeout module
lines and all branches.

Jira NVGPU-4388

Change-Id: I3b3855e6710073c1f878a2f7155a975373094da1
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264345
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
6ef960dbc7 gpu: nvgpu: unit: nvgpu.hal.fifo.ramfc unit test 
This unit test covers most of the nvgpu.hal.fifo.ramfc module lines and
all branches.

Jira NVGPU-4390

Change-Id: I7ef596089deab6fdb351f239124e59dc416a3aa7
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260493
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
9c7051d37f gpu: nvgpu: unit: nvgpu.hal.fifo.ramin unit test 
This unit test covers most of the nvgpu.hal.fifo.ramin module lines and
almost all branches.

Jira NVGPU-4391

Change-Id: Iaae4240305822707dd6446cec0ecc9e833ebffdc
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259638
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
0ca906a6ad gpu: nvgpu: unit: fifo: fifo unit test 
This unit test covers most of the nvgpu.common.fifo.fifo module lines
and almost all branches.

Jira NVGPU-3697

Change-Id: I5722277a3e1630a902f63b707eb3de1c4e1876b0
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2237796
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
917fb2e2df gpu: nvgpu: unit: fifo: channel unit test 
This unit test covers remainder of the nvgpu.common.fifo.channel module
lines and branches.

Jira NVGPU-3696

Change-Id: I590faac1e4340d8fa2e5a7e591249128ec2b8760
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2241973
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
cb273476b6 gpu: nvgpu: unit: branch coverage for tsg 
Cover remaining branches for:
- nvgpu_tsg_abort
- nvgpu_tsg_unbind
- nvgpu_tsg_mark_error

Jira NVGPU-4673

Change-Id: I9dacbf286f1a63cb4c82854984d83b6b9d1fcde3
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2266485
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
fb6fec4e3e gpu: nvgpu: modify unit tests to resolve failures 
Currently, GVS is failing intermittently for some tests in nvgpu-runlist
and hal/mm/mmu_fault.
This patch resets gk20a structure at the end of each mmu_fault test. The
test_runlist_reload_ids and test_runlist_update_locked tests are
modified to use fifo support environment initialized for nvgpu-runlist
unit test.

Bug 2791755

Change-Id: I0b69b4f216f8f820b0a480ed76170b523b434bef
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265676
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
a5470fab90 gpu: nvgpu: unit: branch coverage for gp10b engine HAL 
Add remaining branch coverage for:
- gp10b_engine_init_ce_info (invalid enum read from dev info).

Jira NVGPU-4673

Change-Id: Ibeb673374f547d18a9897eb9dedc7502345461b2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265793
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
8ea850ccb6 gpu: nvgpu: unit: branch coverage for gv100 engine HAL 
Add remaining branch coverage for:
- gv100_dump_engine_status (case w/ no engine)

Jira NVGPU-4673

Change-Id: I1d1eb61752d00a427e79f92f470ff072253791e1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265792
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Nicolas Benech
b682091b13 gpu: nvgpu: SWUTS: clean up test types 
Apply the following changes to test types:
* "Init" --> "Other (setup)"
* "Coverage" --> Removed since it's implied for all tests
* "Feature based" --> "Feature"
* "Boundary Value analysis" and "Boundary values based" --> "Boundary values"
* "Error guessing based" --> "Error guessing"

JIRA NVGPU-3510

Change-Id: I3a9c0c59e6ad806f3479caa5e9a62f4d89f76923
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265670
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
a50802510f gpu: nvgpu: unit: improve coverage for gv11b pbdma HAL 
Improve branch coverage for the following HALs:
- gv11b_pbdma_handle_intr_0 (add error cases for report_pbdma_error)
- gv11b_pbdma_handle_intr_1 (add HCE interrupt case)

Jira NVGPU-3694
Jira NVGPU-4673

Change-Id: I658a7c270af16152ccb6a0b19da1fa8c68e9c2ec
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263669
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
31d689d489 gpu: nvgpu: unit: improve coverage for gm20b pbdma HAL 
Add unit test for the following HAL:
- gm20b_pbdma_get_ctrl_hce_priv_mode_yes

Jira NVGPU-3694
Jira NVGPU-4673

Change-Id: Ie6c0266753877b5fe7a5c32bf6b971d1ef34d724
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263651
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
569b781cb2 gpu: nvgpu: unit: skip falcon dump for fifo intr 
Register address space for falcon is not registered
and g->ops.gr.falcon.dump_stats is triggering multiple
ABORTs while testing gv11b_fifo_intr_0_isr.

Use stub for g->ops.gr.falcon.dump_stats.

Jira NVGPU-4386

Change-Id: I6fb2b9b59f533626fce49bf4d3ff72cb8a1a6c44
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264850
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Antony Clince Alex
81720e81fa nvgpu: userspace: update tests to use mock-iospace library 
Remove mocked IO space definitions from units like fifo and gr, instead
get these from mock-iospace library.

Jira: NVGPU-4520

Change-Id: I397e0bccdb4f744d9dd7fb57d2a2a504abcc618b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261826
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
359fc35fa8 gpu: nvgpu: unit: fifo: runlist unit test 
This unit test covers most of the nvgpu.common.fifo.runlist module lines
and almost all branches.

Jira NVGPU-3699
Jira NVGPU-4135

Change-Id: Ie15579a3c5f7903c2e25ba973078636edea712c9
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2227154
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00