Commit Graph

276 Commits

Author SHA1 Message Date
Sunny He
4074484f75 gpu: nvgpu: gv11b: Reorg debug HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch covers the debug
and dbg_session_ops sub-modules of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I23cda2fbb47fb41975a4a938e352a7427853be94
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514820
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-13 00:09:09 -07:00
Sunny He
4e290320fd gpu: nvgpu: gv11b: Reorg mc HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the mc
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I1a5abde46bf079c206dfdf9f8ee35df048565c49
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509603
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-13 00:09:09 -07:00
Sunny He
aade61eff9 gpu: nvgpu: gv11b: Reorg falcon HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
falcon sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: If980fcd2605a445bd623a5fcca8262826ce289c4
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514013
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-13 00:09:08 -07:00
Sunny He
c9b92595b2 gpu: nvgpu: gv11b: Reorg misc HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch covers the lone
function pointers of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I098559103ef280faca4e82708bb47b9b37057cfd
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1510390
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-07-06 10:54:57 -07:00
Seema Khowala
56eaeab512 gpu: nvgpu: gv11b: sm stride litter added
Required to support multiple SM

JIRA GPUT19X-75

Change-Id: I1fd0530550ae14270a5e746d2efbf3e913ac4c3e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1475985
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
2017-06-29 13:28:53 -07:00
Sunny He
a64984e759 gpu: nvgpu: Reorganize ltc HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the ltc
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: If8760efb7d8e94b63dc6f1fe9efec4ddf49c0b29
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1507563
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-06-27 10:44:06 -07:00
Deepak Nibade
8da78a9fa7 gpu: nvgpu: include <nvgpu/debug.h>
Include <nvgpu/debug.h> explicitly wherever
the debug operations are used

Jira NVGPU-62

Change-Id: I1845e08774b7c211e7fd954937708905f905e069
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1492818
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2017-06-02 06:53:35 -07:00
Seema Khowala
b7af57e41b gpu: nvgpu: gv11b: init priv ring HAL
Initialize priv ring HAL.

Bug 1846641

Change-Id: I738489627e76855328bb2d5ffb2fac1ec8c53dc8
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1473698
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-05-12 10:19:52 -07:00
Mahantesh Kumbar
2266270e2a gpu: nvgpu: init interface layer support for PMU falcon
Change-Id: Iadd72196ed7df7384b1ecdc06ecd98828061fd3e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1473685
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-05-02 23:36:07 -07:00
Terje Bergstrom
e1c27d4e84 gpu: nvgpu: gv11b: Use new clk HAL
Use the new clk HAL to request clock rate instead of direct calls
to Clock Framework. This cuts one direct dependency to Linux APIs.

Also change the HAL to not clear clk ops after they've been
initialized.

JIRA NVGPU-16

Change-Id: I1ab3eac8268f1f3f3305d49782c6a0eb57c6d617
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463536
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
2017-04-24 00:13:39 -07:00
Seema Khowala
1c1b01d067 gpu: nvgpu: gv11b: init css ops
Bug 1870532

Change-Id: Ib8d61e92ad825b9ae5345f62ed2df343b50231b0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1464994
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-04-19 12:16:37 -07:00
Terje Bergstrom
9773dbf905 gpu: nvgpu: Remove unnecessary use of dev_name()
Move the name field from struct gpu_ops up to struct gk20a. The field
is not a function op, so it doesn't belong in gpu_ops.

Replace all uses of dev_name() with use of g->name when possible.

JIRA NVGPU-16

Change-Id: I053aeb256f591af2ea9ef5094a20e33a395cdd33
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1328535
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-03-28 12:05:03 -07:00
Seema Khowala
173cf315ad gpu: nvgpu: gv11b: hal should use gv11b_init_bus
gk20a_init_bus should not be used for gv11b hal init as
bar1_bind is not supported.

Change-Id: I59b6e991b12d8355b1f54ae3eaf78dc94ca6d767
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1327171
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-24 09:08:28 -07:00
Terje Bergstrom
d409d7ebc1 gpu: nvgpu: Add bus HAL
Add bus HAL and separate bus related functions from mm_gv11b:
timer access.

Change-Id: I311f258857238233103688fb653d27e4e79005a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323354
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-23 08:44:12 -07:00
seshendra Gadagottu
207e2ac7d1 gpu: nvgpu: gv11b: reading max veid number
To get maximum number of subctx, sw should read
NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT instead of
LITTER_NUM_SUBCTX.

JIRA GV11B-72

Change-Id: I4d675ba49d8a600da77e7b60da449d9e5ba48971
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1309591
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-27 10:03:23 -08:00
seshendra Gadagottu
30e1647ddf gpu: nvgpu: gv11b: add regops whitelists
Add regops whitelists for gv11b.

JIRA GV11B-35

Change-Id: I0ff5172c5b693250efb0523106632b3746383dcb
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1295401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-27 17:29:57 -08:00
Alex Waterman
4b09997772 nvgpu: gpu: HW header update for Volta
Similar HW header update as has been done for all the other chips.
HW header files are located under:

  drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/

And can be included like so:

  #include <nvgpu/hw/gv11b/hw_gr_gv11b.h>

Bug 1799159

Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284433
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-24 15:15:16 -08:00
seshendra Gadagottu
35969806d2 gpu: nvgpu: gv11b: add clock gating prod settings
JIRA GV11B-15

Change-Id: I38d8cbda33f9c4e8b44ca227cd5ea5fef346bfbd
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1266705
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2016-12-21 12:38:20 -08:00
seshendra Gadagottu
7b67abb2ed gpu: nvgpu: gv11b: support for new littler values
Add support for new litter values:
GPU_LIT_NUM_SUBCTX
GPU_LIT_NUM_SM_PER_TPC

Also updated get_litter_value api to use int
instead of enum type.

JIRA GV11B-21

Change-Id: Ide06245d03743e2d757d27d045701beb25b6707b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1254857
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-11-17 12:07:51 -08:00
seshendra Gadagottu
e1bcaa33ab gpu: nvgpu: gv11b: add dbg_session_ops
JIRA GV11B-21

Change-Id: Ib9c099fb0f9cf910bd5abfc9fd6010803b52c9f8
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1244768
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-11-01 14:04:18 -07:00
Seema Khowala
0b05d33d8a gpu: nvgpu: gv11b : add mm and tsg init
Bug 1735760

Change-Id: I6b33b38ed555759a57ad170e7f75839df51da228
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1207273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-10-14 08:11:17 -07:00
Seema Khowala
32fe739f68 gpu: nvgpu: gv11b: updated hal and gpu_ops
Added init_fb, init_fifo and get_litter_values.
Also initialized read_ptimer

Bug 1735760

Change-Id: Ia1665d60392e9cc58db4cc3f292597aeaea0c718
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1177174
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
2016-07-25 17:10:34 -07:00
Lakshmanan M
6f24a76660 gpu: nvgpu: Add multiple engine and runlist support
This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt support for
   Volta GPU series
5) Removed hard coded engine_id logic and
   made generic way
6) Code cleanup for readability

JIRA DNVGPU-26

Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1156023
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-07 12:31:40 -07:00
Seshendra Gadagottu
66f64c86a8 gpu: nvgpu: gv11b: fix sparse warnings
Fixed following sparse warnings:
drivers/gpu/nvgpu/gv11b/gv11b.c:21:5: warning:
symbol 'gv11b_init_gpu_characteristics' was not declared. Should it be static?
drivers/gpu/nvgpu/gv11b/hal_gv11b.c:36:5: warning:
symbol 'gv11b_init_hal' was not declared. Should it be static?
drivers/gpu/nvgpu/gv11b/gr_gv11b.c:766:5: warning:
symbol 'gr_gv11b_alloc_buffer' was not declared. Should it be static?

Bug 200088648

Change-Id: I327f9d69bf1853727d74d2c125cfab54c2f0e5b0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1128299
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
2016-04-19 08:55:16 -07:00
Seshendra Gadagottu
c84ddceda6 gpu: nvgpu: gv11b: sm priv reg related changes
Included all basic ops for gv11b and updated
sm related functions to include new priv register
addresses.

Bug 1735757

Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1126961
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-04-16 07:48:28 -07:00
Seshendra Gadagottu
55a5c57bc1 gpu: nvgpu: gv11b: added initial source code
Bug 1735757

Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1122123
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
2016-04-13 08:15:13 -07:00