MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: I8c9ad786a741b78293d0ebc4e1c33d4d0fc8f9b4
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921260
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-Added method nvgpu_tu104_acr_ahesasc_sw_init()
to set ACR-AHESASC properties.
-Added method nvgpu_tu104_acr_asb_sw_init() to
set ACR-ASB properties.
-Modified method nvgpu_tu104_acr_sw_init() to
call ACR AHESASC/ASB init & set bootstrap_owner
to LSF_FALCON_ID_GSPLITE by removing older support
of default ACR executing on SEC2.
-Added method tu104_bootstrap_hs_acr to execute
ACR AHESASC & ASB ucode.
-Execute ACR-AHESASC(ACR hub encryption setter and
signature checker) on SEC2 falcon to copy ucode
blob from non-wpr to wpr & lockdown wpr then
perform signature verification of LS falcon ucode
whitout doing any LS flacon bootstrap.
-Once first stage of ACR is successful then execute
ACR-ASB(ACR SEC2 booter) on GSP falcon to bootstrap
SEC2-RTOS on sec2 falcon to perform PMU & GR
falcons bootstrap.
-Enable SEC2 RTOS support by setting
NVGPU_SUPPORT_SEC2_RTOS to true
-Added tu104 ACR remove support to clear
allocated space
JIRA NVGPUT-134
Change-Id: I2d1777af83feda5e8f6845876177cce062c43ace
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918937
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add new separate unit common/perf/cyclestats_snapshot.c and add
corresponding header file include/nvgpu/cyclestats_snapshot.h
This unit is h/w independent and simply calls gops.perf.* HALs
exposed by perf unit to do the h/w configurations
Also remove gv11b/css_gr_gv11b.* files as h/w specific sequence
implemented in them is already moved to perf unit
Rename all cyclestats_snapshot HALs in the form nvgpu_css_*()
Jira NVGPU-1103
Change-Id: I303f6becb313ac918e06c495a5fe299947a1f0b1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1916652
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add Turing specific common, unit, hardware header files
Make all the Makefile and Makefile.sources changes to compile
all Turing specific code
Bug 200454999
Change-Id: I62ebff5c078b4b8817fc83ea0e4ee3cfffe668dc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917983
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
