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10 Commits

Author SHA1 Message Date
Alex Waterman
76b78b6fdc gpu: nvgpu: Remove nvgpu_gpuid_t18x.h 
Remove nvgpu_gpuid_t18x.h since this file is now visible. Migrate
the relevant definitions and defines into their expected places and
make the code use the real defines. No longer is hiding t18x specific
stuff necessary.

Bug 1799159

Change-Id: I47fa2392e46fdb7aacc70aeb0cc8c3f5ca0dc22f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1300976
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-03-02 18:48:41 -08:00
Thomas Fleury
f48a806cf0 gpu: nvgpu: remove BIT macros from header file 
Jira EVLR-472

Change-Id: I791f4647330bfea931da7ea6ffed95b8334b4817
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1172097
(cherry picked from commit 5b41dea91208bba53ba87be1e732c85d177a8ad3)
Reviewed-on: http://git-master/r/1177825
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
 2016-12-27 15:26:18 +05:30
Terje Bergstrom
3d0f9a7517 gpu: nvgpu: Add support for gp104 and gp106 
Add support for chips gp104 and gp106.

Change-Id: Ied5f239bdd0ec85245bce1fb6ef51330871d0f05
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120465
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
 2016-12-27 15:26:16 +05:30
Deepak Nibade
6113c679a9 gpu: nvgpu: API to set preemption mode 
Separate out new API gr_gp10b_set_ctxsw_preemption_mode()
which will check requested preemption modes and take appropriate
action for each preemption mode
This API will also do some sanity checking for valid
preemption modes and combinations

Define API set_preemption_mode() for gp10b which will set the
preemption modes passed as argument and then use
gr_gp10b_set_ctxsw_preemption_mode() and
update_ctxsw_preemption_mode() to update preemption mode

Legacy path from gr_gp10b_alloc_gr_ctx() will convert
flags NVGPU_ALLOC_OBJ_FLAGS_* into appropriate preemption modes
and then call gr_gp10b_set_ctxsw_preemption_mode()

New API set_preemption_mode() will use new flags
NVGPU_GRAPHICS/COMPUTE_PREEMPTION_MODE_* and set and update
ctxsw preemption mode

In gr_gp10b_update_ctxsw_preemption_mode(), update graphics
context to set CTA premption mode if mode
NVGPU_COMPUTE_PREEMPTION_MODE_CTA is set

Also, define preemption modes in nvgpu-t18x.h
and use them everywhere
Remove old definitions of modes from gr_gp10b.h

Bug 1646259

Change-Id: Ib4dc1fb9933b15d32f0122a9e52665b69402df18
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1131806
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:24:54 +05:30
Deepak Nibade
a94e6e72e6 gpu: nvgpu: add T18x specific event ids 
Add CILP preemption started/completed event ids

Bug 200089620

Change-Id: Ie78c9fbe517fd18c4438b6fc06d4c1cf046ba586
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1030777
(cherry picked from commit 065f672020942d377fe3f2388f9daa058406110a)
Reviewed-on: http://git-master/r/1120288
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
 2016-12-27 15:22:11 +05:30
Sami Kiminki
58adb7385d gpu: nvgpu: Determine ECC-enabled units for GP10B 
Determine ECC-enabled units for GP10B by reading fuses/registers.

Bug 1637486

Change-Id: I6431709e3c405d6156dd96438df14d4054b48644
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/780992
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120463
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:11 +05:30
Terje Bergstrom
634acd7422 gpu: nvgpu: Expose preemption flags to user space 
Expose CILP and GFXP flags to user space ioctl
NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX.

Bug 200111328

Change-Id: I10931db2babd3222e308fd491824d95204355ff3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/748932
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:06 +05:30
Seshendra Gadagottu
65ef5bc238 gpu:nvgpu: gp10b: update channel_setup_ramfc 
Enable re-playable faults based on characteristics
flags passed in channel_setup_ramfc.

Bug 1645628

Change-Id: I7176efb3e5af9fefe5fb92cd5b49eb295e8e2c4a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/743382
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:06 +05:30
Deepak Nibade
022d8a602c include: uapi: nvgpu: add flag for IO coherence 
Add below flag for struct nvgpu_as_map_buffer_ex_args
to specify IO coherence
NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT

Bug 1605653

Change-Id: Id5c8195c37c48cff7ec013c6b4b4d9168d972b8e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/713104
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:04 +05:30
Kenneth Adams
16c511220e gpu: nvgpu: t18x, gp10b framework 
This change adds gp10b to the nvgpu build as
well as enabling CMA for buffer allocation.

Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76
Signed-off-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553324
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30