Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.
For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.
JIRA NVGPU-4336
Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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To enable ecc interrupts early during nvgpu_finalize_poweron, ecc
support has to be enabled early. ecc support was being initialized
together for GR, LTC, PMU, FB units late in the poweron sequence.
Move the ecc init for each unit to respective unit's init functions.
And separate out the hal ecc functions from GR ecc unit to
respective hal units.
JIRA NVGPU-4336
Change-Id: I2c42fb6ba3192dece00be61411c64a56ce16740a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2239153
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This function gets the GPU chip architecture, implementation and
revision information by reading the MC boot register, hence it
is more suited to be located in HAL files.
test_check_gpu_state is now being run after test_hal_init as the
gops.mc needs to be initialized for test_check_gpu_state subtest.
JIRA NVGPU-2524
Change-Id: I85355af11d3505a9eb4f10a3fe4e6d9b56285047
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226018
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gk20a.h will include gops_mc.h to contain the mc ops definitions. Add
doxygen comments for the HAL functions that are called directly.
Also move mc_gp10b_intr_pmu_unit_config to non-fusa HAL file.
JIRA NVGPU-2524
Change-Id: I4f326332d7842211b004b372d79fac9fe6ed40e7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226017
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Sometimes nvgpu_sw_quiesce_thread does not get a
chance to run before common.init unit tests complete.
When it finally gets scheduled, related gk20a
context is invalid and it crashes in the pthread
wrapper.
Make sure nvgpu_sw_quiesce_thread has started in
nvgpu_sw_quiesce_init_support, to avoid such issues.
Bug 2732985
Change-Id: I0a46f271a926b5f0c203b465f69556b2b46d96c5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2222560
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Add NVGPU_INIT_TABLE_ENTRY for nvgpu_sw_quiesce_init_support.
Add g->sw_quiesce_init_done to avoid multiple initializations,
and check if deinit is needed in nvgpu_sw_quiesce_remove_support.
This avoids issues in common.init unit tests.
Jira NVGPU-4089
Change-Id: Ife3aa43d5f1f86899a895e4576e38ecc28a8e371
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217779
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For MMU and PBDMA faults, error notifier needs to be set
before entering SW quiesce. Otherwise it ends up with
default NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT.
Added nvgpu_rc_mmu_fault to:
- call g->ops.fifo.recover when recovery is enabled
- set MMU error when recovery is disabled
Updated nvgpu_rc_pbdma_fault to set PBDMA error when
recovery is disabled as well.
Wait for deferred interrupts to complete before actually
entering SW quiesce state, to make sure error notifier has
been set.
Jira NVGPU-4127
Change-Id: Ia84c723e021e397391c6c609d4bb96c06afdcc47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210909
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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IRQs can get triggered during nvgpu power-on due to MMU fault, invalid
PRIV ring or bus access etc. Handlers for those IRQs can't access the
full state related to the IRQ unless nvgpu is fully powered on.
In order to let the IRQ handlers know about the nvgpu power-on state
gk20a.power_on_state variable has to be protected through spinlock
to avoid the deadlock due to usage of earlier power_lock mutex.
Further the IRQs need to be disabled on local CPU while updating the
power state variable hence use spin_lock_irqsave and spin_unlock_-
irqrestore APIs for protecting the access.
JIRA NVGPU-1592
Change-Id: If5d1b5e2617ad90a68faa56ff47f62bb3f0b232b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203860
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Change nvgpu_finalize_poweron() to call the subunit init functions by
using a table. The table is local to nvgpu_finalize_poweron() since the
function pointers are stored at runtime in the gk20a struct during HAL
init. The table also includes a field for checking an enable flag before
calling the init op, if required.
The primary motivation for this change is to reduce CCM for
nvgpu_finalize_poweron(). This change reduced the TCC metric from 40 to
10.
The init unit test is disabled until it can be updated to match the new
design.
JIRA NVGPU-3980
Change-Id: Ic93d3fdd185cc7feb883c898284e15b251277a8b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202974
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Remove the second parameter for the nvgpu_bios_sw_init()
function so the function only requires the gk20a object. The
g->bios was always passed for this parameter. And this makes the
API signature match the other init functions in the driver.
JIRA NVGPU-3980
Change-Id: Id70e2b6b3a9b2705815591d02730d2d2620771c0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202972
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Remove the second parameter for the nvgpu_init_sec2_setup_sw()
function so the function only requires the gk20a object. The
g->sec2 was always passed for this parameter. And this makes the
API signature match the other init functions in the driver.
JIRA NVGPU-3980
Change-Id: I22f526d961da44da64d563f5f3136c62cf9f4adf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202970
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Remove the second parameter for the pmu_early_init() and pmu_init()
functions so they only require the gk20a object. The g->pmu was always
passed for this parameter. And this makes the API signature match the
other init functions in the driver.
JIRA NVGPU-3980
Change-Id: Iae9361a5f14bc5c1d02f4ddb6583f30b71b22d59
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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GR tick frequency needs to be set to MAX value for profiler
use cases for gp10b/gv11b/tu104 chips.
Add new HAL g->ops.ptimer.config_gr_tick_freq() that configures GR
tick frequency to MAX value and call this HAL in GPU poweron path.
This support is not needed in safety build, so compile everything
only if CONFIG_NVGPU_DEBUGGER is enabled
Bug 200289214
Change-Id: Id8378540cc67ca0041b56990f8676e3a105403a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195163
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For safety build, nvgpu driver should enter SW quiesce state
in case an uncorrectable error has occurred. In this state, any
activity on the GPU should be prevented, without powering off the GPU.
Also, a minimal set of operations should be used to enter SW quiesce
state.
Entering SW quiesce state does the following:
- set sw_quiesce_pending: when this flag is set, interrupt
handlers exit after masking interrupts. This should help mitigate
an interrupt storm.
- wake up thread to complete quiescing.
The thread performs the following:
- set NVGPU_DRIVER_IS_DYING to prevent allocation of new resources
- disable interrupts
- disable fifo scheduling
- preempt all runlists
- set error notifier for all active channels
Note: for channels with usermode submit enabled, userspace can
still ring doorbell, but this will not trigger any work on
engines since fifo scheduling is disabled.
Jira NVGPU-3493
Change-Id: I639a32da754d8833f54dcec1fa23135721d8d89a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2172391
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Change the directly called init functions to function pointers in the
HAL. This makes it more consistent. This also allows for writing more
comprehensive unit tests for nvgpu.common.init.
JIRA NVGPU-2239
Change-Id: I05d739a8f8a2e7d385322d93154206eb0bfddc10
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2173920
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CE app functionality from nvgpu is non-safe for igpu. CE engines init
/reset/cg related functionality is required in safety. Hence move the
CE app logic under CONFIG_NVGPU_DGPU flag and update the sources
accordingly.
JIRA NVGPU-3814
Change-Id: I37aa00b1184baccd5fe569ec315be60ac42dac9b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168956
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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- In GV11B, read fuse_status_opt_tpc_gpc register
to read which TPCs are floorswept.
- The driver will also read sysfs node: tpc_pg_mask
- Based on these two values "can_tpc_powergate" will
be set to true or false and mask will be used to write to
fuse_ctrl_opt_tpc_gpc register to powergate the TPC.
- can_tpc_powergate = true indicates that the mask value
sent from userspace is valid and can be used to power gate
the desired TPC
- can_tpc_powergate = false indicates that the mask value
sent from userspace is not valid and cannot be used to
power gate the desired TPC.
Bug 200532639
Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2170736
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If CONFIG_NVGPU_CE is disabled, nvgpu right now does not even reset
the CE engines or initialize prod values.
This ultimately needs to be fixed by adding appropriate initialization
for CE engines even if CONFIG_NVGPU_CE is disabled.
For now, add the code to at least reset CE engines if CONFIG_NVGPU_CE
is disabled
Bug 2526212
Change-Id: Id0a6fbfe44ef7af62715bcee65bef056359f1c19
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165861
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files
JIRA NVGPU-3418
Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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- Fix Rule 16.1 and 16.6 violations:
Every switch statement shall have at least two
switch-clauses
- Fix Rule 15.6 violations:
The body of an iteration statement shall be a
compound statement.
- Fix Rule 17.7 violations:
The return value of a non-void function shall
be used.
JIRA NVGPU-3546
Change-Id: I475d185945f0998d4d359f4b9ded6e983474f01f
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127923
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renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0
JIRA NVGPU-3418
Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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