Building NVGPU against the current upstream mainline kernel is failing
and errors such as the following are seen.
ERROR: modpost: module nvgpu uses symbol dma_buf_map_attachment from
namespace DMA_BUF, but does not import it.
ERROR: modpost: module nvgpu uses symbol dma_buf_detach from namespace
DMA_BUF, but does not import it.
ERROR: modpost: module nvgpu uses symbol dma_buf_vmap from namespace
DMA_BUF, but does not import it.
Following upstream commit 16b0314aa746 ("dma-buf: move dma-buf symbols
into the DMA_BUF module namespace"), it is now necessary to import the
DMA_BUF module namespace into the NVGPU driver to fix this.
Change-Id: I901b74cea692a5e0d66a190d01fe74a55aaf4431
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2621641
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GVS: Gerrit_Virtual_Submit
Start transitioning from an assumption of a single runlist buffer to the
domain based approach where a TSG is a participant of a scheduling
domain that then owns has a runlist buffer used for hardware scheduling.
Concretely, move the concept of a runlist domain up to the users of the
runlist code. Modifications to a runlist need to specify which domain is
modified.
There is still only the default domain that is created at boot.
Jira NVGPU-6425
Change-Id: Id9a29cff35c94e0d7e195db382d643e16025282d
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2621213
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- The hardware is designed in such a way that
if GR engine is not out of reset, it still takes clock.
- This causes ELCG feature to not engage correctly.
- So for iGPU, SW should bring all supported GR
engines out of reset during gpu boot, if MIG feature
is not enabled.
- This will help low power feature like elcg to
engage correctly and improve dynamic power savings.
- For dGPU, all GRs are out of reset by default by dev init.
Bug 200778542
Change-Id: I5f3519f73b4aaf1804fd112f28fe980f58181cd8
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2613718
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Below error notifier message is not really warning/error as that
is user triggered reset and the notifier value set is already
consumed by userspace hence limit this message to INFO type.
nvgpu: 17000000.gp10b nvgpu_set_err_notifier_locked:142 [ERR] error notifier set to 43 for ch 460
Bug 3344409
Change-Id: Ia41cc85f30111ef72994f3ce8e5113e881c06b1b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2620974
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Delete an unnecessary check of the active_channels bitmap when
attempting to bind a channel to a TSG. There is already a verification
that the channel must not be a part of a TSG; if it's not, it cannot be
set in the bitmap. All channels become active via a parent TSG, but the
activity check predates this design.
A channel is bound to a TSG early before setting up its gpfifo etc. and
mandatory membership of a TSG is one of the setup_bind prechecks.
Jira NVGPU-6425
Change-Id: Id34686f198db0a0265ffd6a49a0b2e47c37fd5f7
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2621211
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GVS: Gerrit_Virtual_Submit
Move the active_channels and active_tsgs bitmaps from struct
nvgpu_runlist to struct nvgpu_runlist_domain. A TSG and its channels are
currently active as part of a runlist; in the future, a runlist may be
switched from multiple domains that each are a collection of TSGs.
The changes are still internal to the runlist code. Users of runlists
need no modifications.
Jira NVGPU-6425
Change-Id: I2d0e98e97f04b9716bc3f4890cf881735d0ab664
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
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The current runlist code assumes a single runlist buffer to hold all TSG
and channel entries. Create separate RL domain and domain memory types
to hold data that is related to only a scheduling domain and not
directly to the runlist hardware; in the future, more than one domains
may exist and one of them is enabled at a time.
The domain is used only internally by the runlist code at this point and
is functionally equivalent to the current runlist memory that houses the
round robin entries.
The double buffering is still kept, although more domains might benefit
from some cleverness. Although any number of created domains may be
edited in runtime, nly one runlist memory is accessed by the hardware at
a time. To spare some contiguous memory, this should be considered an
opportunity for optimization in the future.
Jira NVGPU-6425
Change-Id: Id99c55f058ad56daa48b732240f05b3195debfb1
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2618386
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As part of the function gp10b_clk_get_freqs, the code walksthrough
the H/W frequency table and populates the gp10b_freq_table by picking
only GP10B_NUM_SUPPORTED_FREQS =
GP10B_MAX_SUPPORTED_FREQS/GP10B_FREQ_SELECT_STEP frequencies at max.
The access-out-of-bounds happen when sel_freq_count reaches
GP10B_NUM_SUPPORTED_FREQS and new_rate equals max_rate, resulting
in one additional update that is beyond the size of gp10b_freq_table
table.
Also, removed the warning as it will never be true.
Bug 3407276
Change-Id: Ic496ccdda1784130e7139bd93d068be58eb60a35
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2617850
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GVS: Gerrit_Virtual_Submit
The macros defined within the C file in the form
(\
fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m() |\
fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb1_sa_data_m() \
)
are difficult to detect correctly in libclang based static analyzers.
As a consequence, Hal Checker might be missing some coverage.
Such masks are converted into a static function format to help
mitigate this issue.
Change-Id: Id43e25abda8db4c79f7f6fc604eb6e76e9f6282c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
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GVS: Gerrit_Virtual_Submit
nvgpu_timeout_init() returns an error code only when the flags parameter
is invalid. There are very few possible values for flags, so extract the
two most common cases - cpu clock based and a retry based timeout - to
functions that cannot fail and thus return nothing. Adjust all callers
to use those, simplfying error handling quite a bit.
Change-Id: I985fe7fa988ebbae25601d15cf57fd48eda0c677
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2613833
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The implementation already exists. This change
adds NVGPU_GR_ZBC_TYPE_STENCIL and plumbs through
the stencil value from NvRmGpuDeviceZbcAddStencil
through NVGPU_GPU_IOCTL_ZBC_SET_TABLE.
Adds cases for querying the stencil values,
enabling NvRmGpuDeviceZbcGetStencilTableEntry.
Bug 3403523
Bug 3395601
Change-Id: I42c9a2967d0433e0bb08343aabeff0fe465f231e
Signed-off-by: Pyarelal Knowles <pknowles@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554963
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Fix PMM litter values for ROP and LTC units.
The ROP unit has been moved from FBP to GPC, hence, introduce new litter
constants:
- GPU_LIT_PERFMON_PMMGPC_ROP_DOMAIN_START
- GPU_LIT_PERFMON_PMMGPC_ROP_DOMAIN_COUNT
Previous PMMFBP_ROP litter constants are removed.
Update GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT to 4.
Jira NVGPU-7204
Change-Id: If3b5e278099ac0d503a3535f1b9b328dc105488b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
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nvgpu_locate_pte() can be attempted on an address that is not mapped
yet. When the address is just right, it's possible that the pd entries
haven't been allocated yet; return an error in such case before
accessing the indexed entry.
Bug 200778663
Change-Id: I4f062531d30aec746d6828c2d05c046bc912bd2a
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2606175
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GVS: Gerrit_Virtual_Submit
The gmmu mapping code forgot to clear the already written gmmu entries
if a PD allocation failed in the middle. If nvgpu_set_pd_level() fails
when attempting to map, call it again with the same virt addr but unmap.
This may fail again if we're low on memory, but the already updated
entries are guaranteed to exist and get cleared again.
Ensure that TLB is invalidated even in error conditions since the GPU
may have already accessed the partially written data that is now
unmapped again. Likewise, flush L2 too because unmap happened.
Unify the unmap call a bit so that the gmmu attrs for an unmap are now
in only one place, including the unnecessary cbc_comptagline_mode
assignment as it's not used for unmap.
Bug 200778663
Change-Id: I5cbeb2d3fe445b4660eab7f34b04f6c257699b6d
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2599545
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GVS: Gerrit_Virtual_Submit
GPU HW expects physically contiguous addresses when clearing
the compression bit store in memory. Currently on hypervisor setup,
the DMA_ATTR_FORCE_CONTIGUOUS flag ensures contiguous IPA, but it
is not possible to ensure contiguous physical memory.Disable
compression on virtualized environments until physically contiguous
memory is feasible.
Buffer Metadata support is dependent on compression support.
Move the initialization of NVGPU_SUPPORT_BUFFER_METADATA flag to
common code where NVGPU_SUPPORT_COMPRESSION is initialized.
Bug 200780546
Change-Id: Id94bffc878e275a80948880f0475162d0bb4ddae
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2607830
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- For older chips, nvgpu used to set some registers for ELPG
sequencer settings
- These writes are no longer required post-Turing as these
programming have been updated into the HW default values
itself and the register definitions have been changed to
help improve security as well.
- Set the pmu_setup_elpg HAL to NULL
Bug 200766930
Bug 3389932
Change-Id: I3820b14c8491f8180b2feb28cb38e23462546655
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2607599
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Reduce debug logs printed when gpu_dbg_info or gpu_dbg_fn is set.
- Add gpu_dbg_verbose flag for more verbose debug prints. Update prints
in to ga10b_gr_init_wait_idle(), gm20b_gr_init_wait_fe_idle(),
gv11b_gr_init_write_bundle_veid_state() and
gv11b_gr_init_load_sw_veid_bundle().
- Add gpu_dbg_hwpm flag for hwpm specific debug prints. Update print in
nvgpu_gr_hwpm_map_create().
- Add gpu_dbg_mm for MM specific debug prints. Update prints in
gm20b_fb_tlb_invalidate(), gk20a_mm_fb_flush(),
gk20a_mm_l2_invalidate_locked(), gk20a_mm_l2_flush() and
gv11b_mm_l2_flush().
- Remove gpu_dbg_fn mask print in gr_ga10b_create_priv_addr_table(),
gr_gk20a_get_pm_ctx_buffer_offsets(), gr_gv11b_decode_priv_addr() and
gr_gv11b_create_priv_addr_table().
Jira NVGPU-7183
Change-Id: I9842d567047cb95a42e23b5907ae324214eed606
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2602797
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When error (negative value) with int type is returned from read/write
fops (gk20a_power_node_ops) is read as ssize_t value as expected in
userspace it will be seen as large non-negative number and will
suppress the error.
Make return type for these fops ssize_t.
Also include power_ops.h in power_ops.c. This would have caught the
type mismatch issue.
Bug 3388725
Change-Id: Ie66b0178b31a1b7d147b4f441884bbba3bd2e4d8
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2604342
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Removing SW methods completely requires CUDA changes in perforce.
Because of stage-main and module codelines infrastructure this cannot be
done in single series. Hence keep alive couple of SW methods for CUDA
compatibility until SW methods are removed from CUDA code. SW methods
do not perform any action.
Next steps are for CUDA to stop using SW methods. Once that is
integrated this patch can be reverted to completely remove SW method
support in safety build.
Bug 200748548
Change-Id: I2c70a647bec126bab2d8cac4fe10393be8ba0fb9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2604749
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Improved SDL heartbeat mechanism detects the interrupts triggered by
SW method and treats them as errors. Hence remove the SW method support
completely from safety build. Registers set by SW methods are now set
by default for all the contexts.
Implement new HAL gops.gr.init.set_default_compute_regs() to set the
registers in patch context. Call this HAL while creating each context.
Update gv11b_gr_intr_handle_sw_method() to treat all compute SW methods
as invalid.
Update unit test test_gr_intr_sw_exceptions() so that it now expects
failure for any method/data.
Bug 200748548
Change-Id: I614f6411bbe7000c22f1891bbaf06982e8bd7f0b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2527249
(cherry picked from commit bb6e0f9aa1404f79bcfbdd308b8c174a4fc83250)
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The SEC2 ucode allocation code does not free the struct nvgpu_firmware
data structures used while requesting firmwares - sec2_fw, sec2_desc
and sec2_sig.
The lsfm_free_nonpmu_ucode_img_res() API only frees the 'data' field
of struct nvgpu_firmware, but not the entire struct.
Fix these memory leaks by calling nvgpu_release_firmware() API
after the intended use of allocated struct is achieved.
Bug 200690283
Change-Id: I1ed2e1603455bce65af897a40aa31ccc82fda4b0
Signed-off-by: smadhavan <smadhavan@nvidia.com>
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String parameter to kstrtouint has to be null terminated.
If the input string to gk20a_power_write doesn't have the
terminating null character then gk20a_power_write passed
string without appending null character to kstrtouint.
Fix this by preparing string to occupy null character in
the end after user supplied string characters.
Bug 3388725
Change-Id: I521f879326908e296dd9a32b5781db490d40bdd2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2603985
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Martin Radev <mradev@nvidia.com>
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Introduce nvgpu_gmmu_map_partial() to map a specific size of a buffer
represented by nvgpu_mem, or what nvgpu_gmmu_map() used to do. Delete
the size parameter from nvgpu_gmmu_map() such that it now maps the
entire buffer. The separate size parameter is a historical artifact from
when nvgpu_mem did not exist yet; the typical use is to map the entire
buffer.
Mapping at a certain address with nvgpu_gmmu_map_fixed() still takes the
size parameter.
The returned address still has to be stored somewhere, typically to
mem.gpu_va by the caller so that the matching unmap variant finds the
right address.
Change-Id: I7d67a0b15d741c6bcee1aecff1678e3216cc28d2
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2601788
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