MISRA Advisory Rule 2.3 states that a project should not contain
unused type declarations.
The justification for this rule is that a code reviewer may not
know if such a declaration was left behind inadvertently.
The nvgpu deviation record for Advisory Rule 2.3 states that no such
violations will remain that fit this description.
This change removes several unreferenced typedefs so that this
requirement is met.
JIRA NVGPU-3798
Change-Id: I852b5d1fe8d6beb12e6b93219e3101d806a88a39
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150415
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule 8.6 requires that an identifier with external linkage
shall have exactly one external definition. Fix violation of
Rule 8.6 in kmem unit by moving the prototype of fault injection
related function under respective define.
Jira NVGPU-3293
Change-Id: Iac7099fb4a6e396b97edd1ef10b8dfca3c5df760
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152166
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Add BLCG and SLCG clock gating support for HSHUB unit on gv11b and tu104
Register list for BLCG and SLCG is auto generated with scripts.
Add HAL operations to enable/disable HSHUB clock gating
Re-generate gv11b reglist so that all the manually commented registers
are automatically deleted. Some of the unicast registers are also
deleted. We already have corresponding broadcast registers present.
Bug 2526212
Change-Id: I2654f158daa802bcf992e103ed4a44675aa5fd4d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150199
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Using functional macros instead of static inline functions for defining
hw registers, fields, constants etc lets us not compile the dead code
in the build (non-gv11b for igpu safety build for instance).
This patch updates the all nvgpu hw headers to use define_style instead
of inline_style.
JIRA NVGPU-3733
Change-Id: I2d5d596fcfa0a75ce09444edad0a8c2851ee00dc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150879
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Rule 5.7 doesn't allow an identifier to be reused. This patch renames
identifier 'notification' to resolve this violation.
- Rule 8.3 requires all functions and prototypes to have same parameter
names and type qualifier.
- Rule 10.x necessitates operands to have essential type, and left and
right operands should be of same width.
- Rule 11.9 requires pointers to be compared with 'NULL' instead of '0'.
- Rule 14.4 requires if statement condition to be Boolean type.
- Rule 15.7 needs if-elseif constructs to be terminated with else
statement.
- Rule 16.x requires all switch statements to be well-formed with
unconditional break statement terminate every switch-clause.
- Rule 20.7 requires macro parameters to be enclosed in parentheses.
- Rule 21.x doesn't allow reserved identifier or macro names to be
reused or defined.
This patch fixes above listed violations in common/clk_arb/clk_arb.c.
Jira NVGPU-3740
Change-Id: I871ce240ca7fb0372240a8886a53c8d4c460acea
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2147640
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MISRA Rule 3.1 doesn't allow nested character sequences "//" ot "/*" in
a comment. This patch updates link in comment to remove "//" character
sequence.
Jira NVGPU-3766
Change-Id: Ie07f567b752b39868ed8f3c6c220da5f01a8d259
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2147784
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule 16.x requires switch statements to be well-formed, with
non-empty default clause and unconditional break statement for each
clause.
This patch fixes MISRA Rule violations in nvgpu.common.mm.nvgpu_mem.
Jira NVGPU-3766
Change-Id: I0d19b26d1e6f801dadd25337fa56e6ee898c8da0
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2147783
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Following are removed for safety build by adding
CONFIG_NVGPU_KERNEL_MODE_SUBMIT flag.
1) HAL ops in g->ops.sync.syncpt
add_wait_cmd
get_wait_cmd_size
add_incr_cmd
get_incr_cmd_size
get_incr_per_release
2) g->ops.sync.sema is removed in its entirety and contains the
following ops.
3) The following files are compiled out using the above flag.
hal/sync/sema_cmdbuf_gk20a.c
hal/sync/sema_cmdbuf_gv11b.c
Jira NVGPU-3479
Change-Id: I99ae6913e5fe5707ff9a3e2cf06cee8710def7cc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130352
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The following functions belong to the path of kernel_mode submit and
the flag CONFIG_NVGPU_KERNEL_MODE_SUBMIT is used to compile these out
of safety builds.
channel_gk20a_alloc_priv_cmdbuf
channel_gk20a_free_prealloc_resources
channel_gk20a_joblist_add
channel_gk20a_joblist_delete
channel_gk20a_joblist_peek
channel_gk20a_prealloc_resources
nvgpu_channel
nvgpu_channel_add_job
nvgpu_channel_alloc_job
nvgpu_channel_alloc_priv_cmdbuf
nvgpu_channel_clean_up_jobs
nvgpu_channel_free_job
nvgpu_channel_free_priv_cmd_entry
nvgpu_channel_free_priv_cmd_q
nvgpu_channel_from_worker_item
nvgpu_channel_get_gpfifo_free_count
nvgpu_channel_is_prealloc_enabled
nvgpu_channel_joblist_is_empty
nvgpu_channel_joblist_lock
nvgpu_channel_joblist_unlock
nvgpu_channel_kernelmode_deinit
nvgpu_channel_poll_wdt
nvgpu_channel_set_syncpt
nvgpu_channel_setup_kernelmode
nvgpu_channel_sync_get_ref
nvgpu_channel_sync_incr
nvgpu_channel_sync_incr_user
nvgpu_channel_sync_put_ref_and_check
nvgpu_channel_sync_wait_fence_fd
nvgpu_channel_update
nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_channel_update_priv_cmd_q_and_free_entry
nvgpu_channel_wdt_continue
nvgpu_channel_wdt_handler
nvgpu_channel_wdt_init
nvgpu_channel_wdt_restart_all_channels
nvgpu_channel_wdt_restart_all_channels
nvgpu_channel_wdt_rewind
nvgpu_channel_wdt_start
nvgpu_channel_wdt_stop
nvgpu_channel_worker_deinit
nvgpu_channel_worker_from_worker
nvgpu_channel_worker_init
nvgpu_channel_worker_poll_init
nvgpu_channel_worker_poll_wakeup_post_process_item
nvgpu_channel_worker_poll_wakeup_process_item
nvgpu_submit_channel_gpfifo_kernel
nvgpu_submit_channel_gpfifo_user
gk20a_userd_gp_get
gk20a_userd_pb_get
gk20a_userd_gp_put
nvgpu_fence_alloc
The following members of struct nvgpu_channel are compiled out of
safety build.
struct gpfifo_desc gpfifo;
struct priv_cmd_queue priv_cmd_q;
struct nvgpu_channel_sync *sync;
struct nvgpu_list_node worker_item;
struct nvgpu_channel_wdt wdt;
The following files are compiled out of safety build.
common/fifo/submit.c
common/sync/channe1_sync_semaphore.c
hal/fifo/userd_gv11b.c
Jira NVGPU-3479
Change-Id: If46c936477c6698f4bec3cab93906aaacb0ceabf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127212
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Currently, nvgpu_vidmem_buf_access_memory() accepts u64 size/offset
values to access memory. However, underlying nvgpu_mem read and write
functions truncate size/offset value to u32. So, any VIDMEM buffer
larger than 4GB will be inaccessible above 4GB by userspace IOCTL.
This patch updates nvgpu_mem_rd_n() and nvgpu_mem_wr_n() to accept
u64 size and u64 offset values.
BUG-2489032
Change-Id: I299742b1813e5e343a96ce25f649a39e792c3393
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2143138
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
used.
Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.
Also, change users of ALIGN to pass unsigned types only.
JIRA NVGPU-3515
Jira NVGPU-3411
Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Fix MISRA C-2012 Rule 10.8 error in common.gr unit
misra_c_2012_rule_10_8_violation: Cast from 16 bit width expression
to a wider 64 bit type.
Jira NVGPU-3622
Change-Id: Ie3edbb338c0914f37d0b249845ea014c0ba964d2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140939
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Safety build does not support vidmem. This patch compiles out vidmem
related changes - vidmem, dma alloc, cbc/acr/pmu alloc based on
vidmem and corresponding tests like pramin, page allocator &
gmmu_map_unmap_vidmem..
As vidmem is applicable only in case of DGPUs the code is compiled
out using CONFIG_NVGPU_DGPU.
JIRA NVGPU-3524
Change-Id: Ic623801112484ffc071195e828ab9f290f945d4d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132773
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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- This patch replaces "nvgpu_current_time_ms" with "nvgpu_hr_timestamp_us".
- "nvgpu_hr_timestamp_us" gives timestamp in microseconds and has better
accuracy than "nvgpu_current_time_ms" (which gives timestamp in millisecond)
Bug 200503143
Change-Id: I6a10e8e1b3e8ff842aa23f58bf2ba9344af232a6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125959
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Modify nvgpu_gr_checksum_u32 code from
(u32)(((u64)a + (u64)b) % (U32_MAX))
to nvgpu_safe_cast_u64_to_u32(((u64)a + (u64)b) & (U32_MAX)).
This function returns the last 32bits.
Jira NVGPU-3622
Change-Id: I8d348a624a5930b7ba813b0a74af270b49b03844
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140254
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Right now in PMU we have disabled usage of VFE cached values
as we have seen failures in 5.1.3.0 release. This patch
will send vfe_var dependent masks to PMU which will be
used for initial invalidation of dependent VFE_VAR cached
values. As a result PMU will compute the dependent VARs and
cache them.
NVGPU-3645
Change-Id: I814ae819d77270ac45b97cf2a32726992e6f4af3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137423
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Remove below hals since the corresponding functions are same on all
platforms and they are h/w independent
g->ops.gr.enable_ctxsw()
g->ops.gr.disable_ctxsw()
g->ops.gr.reset()
Call the functions directly at all places
Remove CONFIG_NVGPU_DEBUGGER from places where these functions are
called since they are not debugger dependent
This also helps to disable CONFIG_NVGPU_DEBUGGER and to keep recovery
sequence intact
Jira NVGPU-3506
Change-Id: Id2b208ca23dc4667e78edcd8ad242a8558e0ff64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137255
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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