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23 Commits

Author SHA1 Message Date
Sai Nikhil
7ffbbdae6e gpu: nvgpu: MISRA Rule 7.2 misc fixes 
MISRA Rule 7.2 Definition: A "u" or "U" suffix shall be applied to all
integer constants that are represented in an unsigned type.

This patch adds a "U" suffix to integer literals which are being
assigned to unsigned integer variables. In most cases the integer
literal is a hexadecimal value.

JIRA NVGPU-844

Change-Id: I8a68c4120681605261b11e5de00f7fc0773454e8
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959189
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-01-09 18:49:13 -08:00
Sagar Kamble
5efc446a06 gpu: nvgpu: make all falcons struct nvgpu_falcon* 
With intention to make falcon header free of private data we are making
all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn,
nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct
nvgpu_falcon. Falcon structures are allocated/deallocated by
falcon_sw_init & _free respectively.

While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn,
refactor flcn_id assignment and introduce falcon_hal_sw_free.

JIRA NVGPU-1594

Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968242
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-01-03 02:58:38 -08:00
Sagar Kamble
0f952a1a85 gpu: nvgpu: use FALCON_MAILBOX_0 macro 
One of the mailbox 0 read and write hardcoded mailbox number.
Use the macro instead.

JIRA NVGPU-1459

Change-Id: Ic350c91c2100d09187c69724945dae920c9712c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1961635
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2018-12-03 00:13:23 -08:00
Sagar Kamble
fd332ca6b4 gpu: nvgpu: s/*_flcn_*/*_falcon_* 
There is mixed usage of falcon & flcn in function and data types.
Lets update all with "falcon" for consistency with file names.

JIRA NVGPU-1459

Change-Id: I02dbc866ce2cca009f2e8b87cfe11a919ec10749
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1953793
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-11-21 23:04:36 -08:00
Amurthyreddy
1023c6af14 gpu: nvgpu: MISRA 14.4 boolean fixes 
MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.

Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.

JIRA NVGPU-1022

Change-Id: I61a2d24830428ffc2655bd9c45bb5403c7f22c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943058
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 2018-11-07 10:35:22 -08:00
Amulya
3e6a445310 nvgpu: common: MISRA 10.1 boolean fixes 
Fix violations where a variable of type non-boolean is used as a
boolean in gpu/nvgpu/common.

JIRA NVGPU-646

Change-Id: I64e96e02e9a3d5d5604c4fa52460e0415f484d75
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807128
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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 2018-10-29 14:44:38 -07:00
Mahantesh Kumbar
ec2b3a748f gpu: nvgpu: load dbg mem_unlock bin for dbg board 
-Renamed mem_unlock.bin to mem_unlock_dbg.bin
 for MEM_UNLOCK_DBG_BIN define to load debug bin
 for INT board based on debug signal
 SCP_CTL_STAT_DEBUG_MODE

JIRA NVGPUT-76

Change-Id: I054b187f91ee85b09695869e413e43deccd27e5f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918080
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Tested-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2018-10-16 23:40:40 -07:00
Mahantesh Kumbar
63a0e5a149 gpu: nvgpu: load dgb mem_unlock for GPU-NEXT 
load dgb mem_unlock ucode by default for
GPU-NEXT

Change-Id: I7556a8e729ed5f96552f70d7ddb7d4803018847d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1851063
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2018-10-12 17:35:08 +05:30
Deepak Nibade
83ad80de50 gpu: nvgpu: remove VPR HALs from dGPUs 
gops.fb.dump_vpr_wpr_info() accesses both VPR and WPR registers.
Split this into two different HALs gops.fb.dump_vpr_info() and
gops.fb.dump_wpr_info()

Also unset HALs accessing VPR registers on dGPUs
We don't support VPR on dGPUs

Remove fb_mmu_vpr_info_r() register and all its accessors from
dGPU headers

Bug 2173122

Change-Id: I5b2712f8c5389e422a84c375a7e836add48bfd1c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850947
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 2018-10-12 17:35:08 +05:30
Terje Bergstrom
2c17e71aa1 gpu: nvgpu: Add MC APIs for reset masks 
Add API for querying reset mask corresponding to a unit. The reset
masks need to be read from MC HW header, and we do not want all
units to access Mc HW headers themselves.

JIRA NVGPU-954

Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2018-10-12 17:35:07 +05:30
Mahantesh Kumbar
c2cf2252a9 gpu: nvgpu: Add support to load dbg/prod mem_unlock ucode 
-Add support to load dbg/prod mem_unlock ucode
 based on debug Signal SCP_CTL_STAT_DEBUG_MODE.
-Defined MEM_UNLOCK_PROD_BIN & MEM_UNLOCK_DBG_BIN
 to hold dbg/prod ucode names.

JIRA NVGPUT-76

Change-Id: Ie282a281fe502ada31a69e3b3c734e9a3a725395
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1842880
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2018-10-12 17:35:06 +05:30
Debarshi Dutta
421e64aad7 gpu: nvgpu: move header location of gk20a.h 
Update header path of gk20a.h in files present in common/
to <nvgpu/gk20a.h>

Jira NVGPU-597

Change-Id: I3431dae93ada9bd561454c89a0b99c5292ab4a8d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832024
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 2018-09-25 00:20:25 -07:00
Terje Bergstrom
83efad7adb gpu: nvgpu: Move FB size query to FB 
Vidmem size query was in mm_xxx.c. It involves reading a register from
FB, so move the query to FB HAL.

JIRA NVGPU-1063

Change-Id: I30dfd2c4fdcdd6c841f85aaab7431d52473759bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801425
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2018-09-10 15:23:08 -07:00
Terje Bergstrom
b25d5d86ca gpu: nvgpu: Use debug sig for NVDEC if on dbg SKU 
Debug fused chips do not have production signature. Use debug
signature for memory unlock binary. Requires also exporting a HAL
for checking debug mode from PMU.

Bug 200445202

Change-Id: I7f88ed6db2fe1c614fe9d4074dbf974c3817f453
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809225
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 2018-08-31 18:57:15 -07:00
Tejal Kudav
4940f4c1b4 gpu: nvgpu: Set nvdec mailbox reg 0 to nonzero val 
The scrubber binary after completion updates its return
code in mailbox register 0. The memory unlock code reads
this registers to determine the success of memory scrubbing.
This register is initialized to 0 during nvdec falcon reset.
If the scrubber binary halts due to an error condition, the
return code is not updated and it stays at 0.
Initialize the status register explicitly to non-zero value
helps avoid just false positives.
Add falcon register dump and PC trace to help debug the memory
unlock failures.

Change-Id: I3086dda2a9719c2d0b8a7ae898f1a03bedfa21b0
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808899
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2018-08-31 07:34:22 -07:00
Terje Bergstrom
dd71ad91b9 gpu: nvgpu: Implement own ACR code for scrubber 
Implement HW scrubber specific code for filling in ACR header. The
PMU code relied on PMU debug mode for choosing between dbg/prod
signature, and also introduced a direct dependency from FB to ACR.

Change-Id: I08fa31538bec3dcb5d161a6e7076ffad76129a97
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801418
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2018-08-27 21:44:30 -07:00
Terje Bergstrom
6f57a339ee gpu: nvgpu: gv100: Remove extra UART spew 
Remove extra UART spew in fb_gv100.c. We were using nvgpu_info()
instead of nvgpu_log_info().

Change-Id: Ideb44e492a76ca2f58c14b445bb0a31ebe4c995a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805692
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 2018-08-27 10:23:42 -07:00
Konsta Holtta
3bd47da095 gpu: nvgpu: add missing timer includes 
Many files used declarations from timers.h implicitly via another header
file(s). Add several #includes explicitly to their users.

Jira NVGPU-967

Change-Id: I88b515061db87c69bd85e3655b74d0271a80d9bf
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804611
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 2018-08-24 14:57:57 -07:00
Terje Bergstrom
f062cc5b24 gpu: nvpgu: Remove dependency from FB to Falcon 
FB had a dependency to Falcon headers because it was doing debug
dump of registers. Remove the debug dump to get rid of the dependency.

JIRA NVGPU-1063

Change-Id: I15c259b66ce58fd327e974c8d66b6be764e61fed
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801416
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2018-08-24 14:57:14 -07:00
Srirangan
9e69e0cf97 gpu: nvgpu: common: Fix MISRA 15.6 violations 
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I599cce2af1d6cdc24efefba4ec42abfe998aec47
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795845
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-08-20 05:46:25 -07:00
Vinod G
c9f8f1ea05 gpu: nvgpu: remove utils.h from gk20a.h 
Removed the utils.h include from gk20a.h
utils.h is included in those files which
make use of the macros in utils.h

JIRA NVGPU-1005

Change-Id: Ifb41da58db6ff8682fa6b5dfdd8eda11a751fcac
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1785952
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2018-08-10 18:11:26 -07:00
Debarshi Dutta
82a90170d3 gk20a: nvgpu: Remove io.h dependency from gk20a.h 
In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h

JIRA NVGPU-597

Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2018-07-30 11:24:06 -07:00
Terje Bergstrom
b97bcb3c68 gpu: nvgpu: Move FB to common 
Move all FB HAL implementations to common/fb.

JIRA NVGPU-596

Change-Id: Id4ea09d608f5d6d1b245bddac09ecf1444b8ab30
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769724
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-07-12 20:44:13 -07:00