458 Commits

Author	SHA1	Message	Date
Mahantesh Kumbar	6ed3cffb73	gpu: nvgpu: ACR boot on SEC2 ... ACR/SEC2 methods to support ACR boot SEC2 falcon JIRA DNVGPU-34 Change-Id: I917be1d6c61a1c1ae61a918f50228ea00492cd50 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161122 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>	2016-12-27 15:26:17 +05:30
Mahantesh Kumbar	7b43eac2bc	gpu: nvgpu: ACR interface update for GP104/GP106 ... JIRA DNVGPU-34 Change-Id: Ieb8e73451a5d73480b8d9e29e78b1a273b17d796 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161120 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>	2016-12-27 15:26:17 +05:30
Konsta Holtta	4ded050bd0	gpu: nvgpu: include matching header in mm_gp106.c ... Include mm_gp106.h in mm_gp106.c to bring function declarations visible and to fix a Sparse warning. Bug 200088648 Change-Id: Id76f565021de585bc02a53a01e52084ff70009c2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1161607 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>	2016-12-27 15:26:17 +05:30
Konsta Holtta	8a2be379cd	gpu: nvgpu: detect vidmem configuration from HW ... Read video memory size from hardware during initialization for devices that support it. JIRA DNVGPU-14 Change-Id: I84e1bca0eaac8dc204e1fb82628acc6b52c3e5cc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157212 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>	2016-12-27 15:26:17 +05:30
Lakshmanan M	9454529abe	gpu: nvgpu: Add multiple engine and runlist support ... This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>	2016-12-27 15:26:17 +05:30
Lakshmanan M	642cc7416e	gpu: nvgpu: Add device_info_data support ... Added device_info_data parsing support for pascal GPU series. This is required to identify the (Logical CE) NV_PTOP_DEVICE_INFO_TYPE_ENUM_LCE instance id. (example - CE0, CE1, CE2, CE3, ...) JIRA DNVGPU-26 Change-Id: I35c42cb1d544729e4099db1528c690dd2be025f4 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1151605 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>	2016-12-27 15:26:16 +05:30
Deepak Nibade	85e67e368b	gpu: nvgpu: fix sparse warning ... fix below sparse warning : $TOP/kernel-nvgpu-t18x/drivers/gpu/nvgpu/gp106/pmu_gp106.c:22:5: warning: symbol 'gp106_pmu_reset' was not declared. Should it be static? Bug 200088648 Change-Id: I86120fb6b9733f256c96764a77c6ea4bb636934a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1154452 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>	2016-12-27 15:26:16 +05:30
Terje Bergstrom	3d0f9a7517	gpu: nvgpu: Add support for gp104 and gp106 ... Add support for chips gp104 and gp106. Change-Id: Ied5f239bdd0ec85245bce1fb6ef51330871d0f05 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120465 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>	2016-12-27 15:26:16 +05:30