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217 Commits

Author SHA1 Message Date
Konsta Holtta
bd65e7611f gpu: nvgpu: zbc: disable activity only from ioctl 
Move the fifo engine activity disabling and wait-for-idle from the
lowest-level functions higher, into the ioctl path of zbc operations, so
that the sw initialization path wouldn't call them. During the init
path, the disable isn't necessary, and the code path could result in a
deadlock in the fifo runlist mutex.

Change-Id: I56e73204e288331165358fc9856390f1eb724488
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/715196
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:04 +05:30
Terje Bergstrom
208e2c3353 gpu: nvgpu: gp10b: Fix offset for preemption ptr 
Offset for preemption pointer was calculated incorrectly.

Bug 1617214

Change-Id: I9c1a9ae24dcd523f4ae17eae0a5b07831839fadb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/716528
 2016-12-27 15:22:04 +05:30
Deepak Nibade
3be18b463b gpu: nvgpu: add exception registers to dump 
Add below exception registers to GR dump :
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN

Bug 200078514

Change-Id: I2400e360fea0b3bdcdf5f3dd6ef250867fb191e6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/712481
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:04 +05:30
Kirill Artamonov
ce85eae72a gpu: nvgpu: gp10b: fix swdx_rm_spill size and pointer 
Fixed incorrectly encoded pointer and size.

bug 1525327
bug 1581799

Change-Id: Ie6e94e47c3b11e9d9aa63a70b61e6e89f69e971b
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/713209
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:04 +05:30
Terje Bergstrom
7b70eb224a gpu: nvgpu: gp10b: Enable warnings as errors 
Change-Id: I86de27309ebecd038a7b32c6f86d87ce0156eb14
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/709867
 2016-12-27 15:22:03 +05:30
Deepak Nibade
6cf9d594f0 gpu: nvgpu: gp10b: dump GR status registers 
Add function pointer gr_gp10b_dump_gr_status_regs()
which will enable dumping GR status registers for gp10b

Bug 200062436

Change-Id: Iaecc2f9c9364232079bb03e114f68550bd035372
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/678832
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:03 +05:30
Vijayakumar
83c223ac56 gpu: nvgpu: gp10b: use tight loop for fecs method 
bug 200078367

Change-Id: I9a68e988fa7921276e334c75afa5ee4b15aab464
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/707313
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
4493b6b200 gpu: nvgpu: gp10b: Enable CILP mode for compute 
Allow enabling CILP for compute. Set CTA by default.

Bug 1517461

Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/661298
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
15839d4763 gpu: nvgpu: Implement gp10b context creation 
Implement context creation for gp10b. GfxP contexts need per channel
buffers.

Bug 1517461

Change-Id: Ifecb59002f89f0407457730a35bfb3fe988b907a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/660236
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
5d54f4660c gpu: nvgpu: gp10b: Change order of alpha & beta 
Change order of alpha & attribute buffers in CB. The new order
follows RM.

Change-Id: I2b24daa46055b3bd667a1026c282f74d56882623
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/657907
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
59f267981c gpu: nvgpu: gp10b: Program CB sizes 
Program CB sizes.

Bug 1567274

Change-Id: Idc88f69b70e85bf950af852a9ca80a328d95883f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/654097
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
e5161d1518 gpu: nvgpu: gp10b: Implement SW methods 
Bug 1567274

Change-Id: I6d760eca7ac0931847f9a04a9d4a408519ade511
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/654098
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
230779e25b gpu: nvgpu: gp10b: Calc global context buffer size 
In gp10b we need to limit global context buffer size, and it needs
to be 128b aligned.

Change-Id: I51570e2457a374c09be4d611e683ae30917f9fc0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/657911
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
a83e5281af gpu: nvgpu: gp10b: Define pagepool size 
Bug 1567274

Change-Id: I4369458d3af0c4da32af8a5881c8fe60b11f7632
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606932
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
3cfc020b91 gpu: nvgpu: Write ZBC registers to DSS 
Bug 1567274

Change-Id: Ife98ae512c62bd26450e59338719c7a10635b5dd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601108
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
1e4861a347 gpu: nvgpu: gp10b specific CB callbacks 
Bug 1570662

Change-Id: Icb7e90b1216acfd19bb3027dc9e9844eb08c99d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592101
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Kenneth Adams
16c511220e gpu: nvgpu: t18x, gp10b framework 
This change adds gp10b to the nvgpu build as
well as enabling CMA for buffer allocation.

Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76
Signed-off-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553324
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30