Commit Graph

168 Commits

Author SHA1 Message Date
Seema Khowala
b076c349b2 gpu: nvgpu: gv11b: fix engine context preempt completion
CTX_STATUS_SWITCH: Engine save hasn't started yet, continue to poll

CTX_STATUS_INVALID: The engine context has switched off.  The
   preemption step for this engine is complete.

CTX_STATUS_VALID or CTX_STATUS_CTXSW_SAVE: check the ID field:
  * If ID matches the TSG for the context being torn down, the engine
    reset procedure can be performed, or SW can continue
    waiting for preempt to finish if id is not being torn down.
  * If ID does NOT match, the context isn't running on the engine.

CTX_STATUS_LOAD: check the NEXT_ID field:
  * If NEXT_ID matches the TSG of the context being torn down, the engine
    is loading the context and reset can be performed
    immediately or after a delay to allow the context a chance to load and
    be saved off, or sw can continue waiting for preempt to finish if id
    is not being torn down.
  * If NEXT_ID does not match the TSG ID or CHID then the context is no
    longer on the engine.

SW may alternatively wait for the CTX_STATUS to reach INVALID, but this
may take longer if an unrelated context is currently on the engine or
being switched to.

JIRA GPUT19X-7

Change-Id: I61499f932019de32e0200084c4c41b21a7cbbd2b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1327164
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-26 09:55:16 -07:00
Seema Khowala
40d2f60903 gpu: nvgpu: gv11b: implement init_pbdma_intr_desc fifo ops
Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w
variables for pbdma_intr_0 interrupt masks.

pbdma_intr_0 field changes for gv11b:-
bit 8(lbreq) does not exists in hw.
bit 28 (syncpoint_illegal)is removed in hw.
bit 20 is reused for clear_faulted_error in hw.
bit 24 (eng_reset) and bit 25 (semaphore) always existed in hw
but never handled in s/w. These are added as channel fatal.

JIRA GPUT19X-47

Change-Id: I13673430408f1cf7ef762075a29b94196f79a349
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325401
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-23 09:34:13 -07:00
Seema Khowala
8929fb2b1d gpu: nvgpu: gv11b: implement is_preempt_pending
preempt completion should be decided based on pbdma and
engine status. preempt_pending field is no longer used
to detect if preempt finished.

add a new function to to be used for preeempting ch and tsg
during recovery. If preempt timeouts while in recovery, do not
issue recovery.

JIRA GPUT19X-7

Change-Id: I0d69d12ee6a118f6628b33be5ba387c72983b32a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1309850
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-21 12:08:06 -07:00
Seema Khowala
18a0a89f45 gpu: nvgpu: init intr_0_error_mask fifo ops
mmu fault is now part of hub interrupt

Change-Id: I9ce523d5f11955ac9552510d154eaa2f17a6cbf6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313484
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-20 16:39:49 -07:00
Seema Khowala
679086c42e gpu: nvgpu: gv11b: support debug dump
Added dump for pbdma, engine status, channel status
and ramfc

JIRA GV11B-45

Change-Id: I25442932c61310005fea481455f68ba10c361381
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1302425
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-09 12:23:29 -08:00
Seema Khowala
5e4ca8f5e8 gpu: nvgpu: gv11b: trigger mmu fault is not supported
For gv11b fifo recovery, triggering fake mmu fault is not required.

JIRA GV11B-7

Change-Id: I6c8c9672085dbbbd77e0d991d840c4cc75c2ab43
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313496
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-08 10:48:24 -08:00
Seema Khowala
8d6a05fc57 gpu: nvgpu: gv11b: init is_fault_engine_subid_gpc ops
*client_type_gpc_v moved from fifo to gmmu

JIRA GV11B-7

Change-Id: Icd28a2ac8c0d0ae212cfca9410dfe781972367df
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313435
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-07 02:34:56 -08:00
Seema Khowala
a4ea94f5d1 gpu: nvgpu: init fifo ops for device_info_fault_id
generated hw header for top_device_info_data_fault_id_enum_v
is different between legacy chips and t19x

JIRA GV11B-7

Change-Id: Ia765be740c419c5b2a61b03104b264c51f1e797e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313383
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 08:53:33 -08:00
Seema Khowala
8497f45a2e nvgpu: gpu: gv11b: Remove syncpt protection support
In gv11b sync point support is moved to a shim outside of GPU,
and gv11b does not support sync points anymore. Remove use of
the sync point protection.

JIRA GV11B-47
JIRA GV11B-2

Change-Id: I70f3d2ce0cfe016453efe03f2bbf64c59baeb154
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1300964
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-13 17:54:28 -08:00
Alex Waterman
4b09997772 nvgpu: gpu: HW header update for Volta
Similar HW header update as has been done for all the other chips.
HW header files are located under:

  drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/

And can be included like so:

  #include <nvgpu/hw/gv11b/hw_gr_gv11b.h>

Bug 1799159

Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284433
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-24 15:15:16 -08:00
seshendra Gadagottu
4f3871309d gpu: nvgpu: gv11b: restore golden context
Restore golden context correctly with subcontext header.
Increase subctx header size to hold complete golden context.
Also fill function pointer for freeing context header.

Bug 1834201

Change-Id: Id8a3437bc437fef02ee15333c1163290217d34d1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1282440
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-20 10:54:17 -08:00
seshendra Gadagottu
4ad2d3aebc gpu: nvgpu: gv11b: support for multiple runlists
Add support for multiple runlists in gv11b.

Bug 1834201

Change-Id: I5a4cb92643626675314b4b61df330cde06e22c9f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1285044
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-16 12:15:30 -08:00
seshendra Gadagottu
67b54c3c76 gpu: nvgpu: legacy support with subcontext
gv11b needs atleast one subcontext to submit work. To support
legacy in gv11b, currently main context is always copied into
subcontext0 (veid0) during channel commit instance.

As part of channel commit instance, veid0 for that channel is
created and relevant pdb and context info copied to vedi0.

JIRA GV11B-21

Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1231169
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-20 15:15:14 -08:00
seshendra Gadagottu
4bac40b5b3 gpu: nvgpu: gv11b: set ce context valid
Set copy engine context valid for channel loaded on
pbdma.

JIRA GV11B-21

Change-Id: I74445dcefe38b52723705c185e6a37c9f56ac2bf
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1254916
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-11-21 08:50:52 -08:00
seshendra Gadagottu
2fd1ee0ca7 gpu: nvgpu: gv11b: update ramfc
Updated ramfc:
 - To include channel veid info
 - Set valid context bit
 - Enabled userd writeback

JIRA GV11B-11

Change-Id: I0e8c62fe0dee02071b0ca60f157151038ab5c09b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1237764
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-10-21 13:44:04 -07:00
seshendra Gadagottu
1a36091fb9 gpu: nvgpu: gv11b: sysmem userd support
For gv11b, userd is allocated from sysmem.
Updated gp_get and gp_put functions to read or
write from sysmem instead of bar1 memory.

In gv11b, after updating gp_put, it is required
to notify pending work to host through channel
doorbell.

JIRA GV11B-1

Change-Id: Iebc52e6ccfc8b9ca0c57b227190e0ce1161076f1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1226613
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-10-11 09:16:04 -07:00
seshendra Gadagottu
8fdf40a849 gpu: gv11b: create modified runlist
Create gv11b runlist for channel and tsg in the new
specified way. Also set runlist entry size for gv11b.

Bug 1735760

Change-Id: Ifd421cd71180e9d02303f4cfc92a59fd74d6d893
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1220258
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-09-21 15:14:00 -07:00
Seshendra Gadagottu
c84ddceda6 gpu: nvgpu: gv11b: sm priv reg related changes
Included all basic ops for gv11b and updated
sm related functions to include new priv register
addresses.

Bug 1735757

Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1126961
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-04-16 07:48:28 -07:00