Multiple non-safe functions under NVGPU_DEBUGGER, NVGPU_CILP and other
config flags were moved to fusa files. Although they are guarded by
the C flags, it makes sense to keep those functions in non-fusa
files. Make this change for all hals.
JIRA NVGPU-3853
Change-Id: I8151b55a60cb50c5058af48bab9e8068f929ac3b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204352
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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This patch addresses misra violations due to SDL error reporting
callbacks. In particular, it addresses the following misra violation:
- misra_c_2012_directive_4_7_violation: Calling function
"nvgpu_report_*_err()" which returns error information without testing
the error information.
JIRA NVGPU-4025
Change-Id: Ia10b6b3fd9c127a8c5189c3b6ba316f243cedf04
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196895
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Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.
The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.
JIRA NVGPU-3820
Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
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Advisory Rule 5.9 states that identifiers that define objects or functions
with internal linkage should be unique.
This change eliminates an Advisory Rule 5.9 violation in our the mmu and
fifo fault handling code involving the 'invalid_str' variable by
renaming it to 'mmufault_invalid_str' and 'ctxsw_status_invalid_str'
respectively.
Jira NVGPU-3178
Change-Id: I9b60c8441fc8e0423151f1bf116d21489af78bf0
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2190084
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INT30-C requires that unsigned integer operations do not wrap.
INT31-C requires checking that data isn't misinterpreted after casting.
INT32-C requires that signed operations do not overflow.
Jira NVGPU-3882
Change-Id: I6b4c1769ec85919f8ec2aa183cba3b7c0ffa1e97
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166124
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Eliminate Advisory Rule 8.11 violations in gmmu_gk20a.h by
removing extern declarations of gk20a_mm_levels_64k[] and
gk20a_mm_levels_128k[].
Advisory Rule 8.11 states when an array with external linkage
is declared, its size should be explicitly specified.
Jira NVGPU-3178
Change-Id: I452a571e0561edbd9f8cd856775563587c201d40
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2162273
GVS: Gerrit_Virtual_Submit
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Reviewed-by: Adeel Raza <araza@nvidia.com>
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Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions.
Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
Rule 14.3 doesn't allow controlling expressions to be invariant;
ensuring that all conditions are possible.
Jira NVGPU-3858
Change-Id: I043a3836c4a2cb9c5a52d3053516c517389f55a2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2162295
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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This change switches nvgpu_timeout_peek_expired() to return a bool
instead of an int to remove advisory rule MISRA 10.5 violations.
MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.
JIRA NVGPU-3798
Change-Id: I5cf9badaf07493e11a639e47ae4cf221700134ff
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155617
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INT-30 requires checking for overflow of arithmetic operations on
unsigned integers.
INT-31 requires bounds checking for unsigned integers cast to
smaller size.
Fix these violations by using the safe ops in nvgpu.common.mm.mm and
nvgpu.hal.mm.mm.
JIRA NVGPU-3848
Change-Id: I2751a14fb1f45d330a92040ac3c7777c52ae9199
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158860
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Fix MISRA errors in hal/mm/gmmu/gmmu_gp10b_fusa.c
Rule 10.6 forbids assignment of u32 expression to u64 target.
This patch fixes this rule by casting the expression to u64.
Rule 20.6 doesn't allow use of preprocessor directives within a macro.
To resolve this patch moves the preprocessor directive before the macro
function call.
Jira NVGPU-3806
Change-Id: Ib7ddf746c801be62d3dd90a6ab7e27c690a60dc6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152065
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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This patch moves MM HALs that are guaranteed to be functionaly safe
into _fusa.c files. HALs that are not part of FUSA are not compiled
anymore when the safety profile is enabled.
Given a HAL source file:
- it may contain only FUSA code, in that case the source file is
simply renamed with the _fusa postfix.
- it may contain only non-FUSA code, in that case the file is left
as-is
- it may contain a mix, in that case the original file will now only
contain non-FUSA code, and all FUSA code will be moved into a new
source file with the _fusa postfix.
JIRA NVGPU-3690
Change-Id: I44c604aef2d72252abb7da1c0ef1210d71a0efa7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140895
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.
This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.
Jira NVGPU-3476
Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
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Below MISRA 17.7 violations are reported in nvgpu.hal.mm.mm,
for nvgpu_timeout_init functions:
misra_c_2012_rule_17_7: The return value of a non-void function
"nvgpu_timeout_init" is unused.
Fix this by asserting that nvgpu_timeout_init is successful, since
it should never fail with NVGPU_TIMER_RETRY_TIMER flag.
Jira NVGPU-3283
Change-Id: I89a6afa5d024683a50dfa5dc277da7fe4a6478bb
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119606
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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MISRA mandates switch clauses to end with an unconditional break
statement. Refactor switch/case in gv100_mm_get_flush_retries
function to set retries in each clause, then return result
at the end of the function.
Refactoring of the switch/case solves MISRA 16.1, 16.3 and 16.6
violations.
Jira NVGPU-3314
Change-Id: Ie051a8f2df805b63a7bef6a55fea3ae011603a0e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118887
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Move the gv11b MMU fault handling code into a new mm.mmu_fault HAL.
Also move the existing gmmu_mmu_fault HAL code into this HAL as they
are basically the same logical entity.
JIRA NVGPU-2042
JIRA NVGPU-1313
Change-Id: I41d3e180c762f191d4de3237e9052bdc456f9e4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109693
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There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.
Much of this is fairly straightforward copy/paste and updates to the
HAL init files.
The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.
JIRA NVGPU-2042
Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
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Move the remaining GMMU HAL related code from the gm20b/, gp10b/,
and gv11b/ directories to new gmmu hal source files.
Also update all makefiles and HAL init code to refelct the new
location of the headers and source code.
JIRA NVGPU-2042
Change-Id: Ic9b85cc547bd0f994ad11042fc4093c517327399
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103672
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Make a hal/mm/gmmu sub-unit for the GMMU HAL code. Also move the
gk20a specific HAL code there. gp10b will happen in the next patch.
This change also updates all the GMMU related HAL usage, of which
there is quite a bit. Generally the only change is a .gmmu needs to
be inserted into the HAL path. Each HAL init was also updated.
JIRA NVGPU-2042
Change-Id: I6c46bdfddb8e021f56103d9457fb3e2a226f8947
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099693
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