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7471 Commits

Author SHA1 Message Date
Thomas Fleury
bdaa8519d5 gpu: nvgpu: unit: improve coverage for gv11b tsg HAL 
Add test for the following HAL:
- gv11b_tsg_enable

Jira NVGPU-4890

Change-Id: Ia79be676098e18ca71f6f9983485bf107c15f37c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280135
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
45a6b873d2 gpu: nvgpu: unit: traceability for fifo 
Fix 'Targets:' statements and/or add explicit tests for:
- gops_fifo.fifo_init_support
- gops_fifo.fifo_suspend
- gv11b_tsg_unbind_channel_check_eng_faulted
- nvgpu_tsg_from_ch
- nvgpu_tsg_alloc_sm_error_states_mem
- nvgpu_tsg_cleanup_sw
- nvgpu_tsg_set_error_notifier
- nvgpu_tsg_enable_sched
- nvgpu_tsg_default_timeslice_us
- nvgpu_tsg_get_from_id
- nvgpu_tsg_disable_sched
- nvgpu_tsg_release_common
- nvgpu_tsg_check_and_get_from_id
- nvgpu_tsg_open_common
- gv11b_pbdma_config_userd_writeback_enable
- gv11b_tsg_deinit_eng_method_buffers

Jira NVGPU-4890

Change-Id: I298b9f18318105cee8dc882767e30729e7106ccc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280134
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
55510f266d gpu: nvgpu: unit: improve coverage for engines 
Improve branch coverage for the following functions:
- nvgpu_engine_get_active_eng_info
- nvgpu_engine_get_ids
- nvgpu_ce_engine_interrupt_mask
- nvgpu_engine_get_gr_runlist_id

Add unit tests for the following functions:
-_nvgpu_engine_get_fast_ce_runlist_id
- nvgpu_engine_is_valid_runlist_id
- nvgpu_engine_id_to_mmu_fault_id
- nvgpu_engine_mmu_fault_id_to_engine_id
- nvgpu_engine_get_mask_on_id
- nvgpu_engine_get_id_and_type
- nvgpu_engine_find_busy_doing_ctxsw
- nvgpu_engine_get_runlist_busy_engines
- nvgpu_engine_mmu_fault_id_to_veid
- nvgpu_engine_mmu_fault_id_to_eng_id_and_veid
- nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id

Jira NVGPU-4511

Change-Id: Ib340df17468ff3447e271a86af9a47a067f6ad11
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2262222
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
45b99f67b2 gpu: nvgpu: remove dead code for runlist_id check 
nvgpu_engine_is_valid_runlist_id already iterates the list of
active engines, therefore the engine_id is already known to
be valid.

Remove call to nvgpu_engine_get_active_eng_info (which iterates
all engines), and fetch f->engine_info[engine_id] instead.
Also remove non-NULL test for engine_info, which could not
be true.

Also make sure to reset num_engines in nvgpu_cleanup_sw, to avoid
accessing uninitialized active_engines_list in unit test corner
cases (targetting init/remove support).

Jira NVGPU-4511

Change-Id: Ia6b904a7f3ca46e5097f06770b4caad317ec967b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2263618
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
3b9630a366 gpu: nvgpu: fuse: use hals instead of direct register reads 
Use fuse hals instead of direct fuse register reads to make
code compatible with multiple chip families.

JIRA NVGPU-4663
JIRA NVGPU-4835
JIRA NVGPU-4856

Change-Id: I15889aee38baf6393d11becb7ed995e9f0fd5897
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279629
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
75be2f3f2c gpu: nvgpu: unit: therm: use gops for HALs 
Switch to calling the gops for the HALs rather than the HAL directly.
Update the SWUTS to reflect this change.
This allows traceability with the SWUD.
Also, move a non-fusa hal to the non-doxygen section for gops_therm.h.

JIRA NVGPU-4818

Change-Id: Ia6a0d3ad94fbb97cdb345bfc89bc7ab3cd4f2d5a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279486
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Philip Elcan
8c40423377 gpu: nvgpu: doxygen: build in extra path too if supplied 
Update Makefile.doxygen to include files from an extra path if provided
by passing EXTRA_PATH to the makefile.

JIRA NVGPU-4818

Change-Id: I4fb45dd929a6c7342f1e6406390c2c379e0b2764
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2278583
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Scott Long
3b4b418330 gpu: nvgpu: fifo: misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from fifo code.

Jira NVGPU-3178

Change-Id: I487d039c5be8024b21ec87d520d86763f9338d2a
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2276793
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
858905aeae gpu: nvgpu: fifo: remove runlist.c dead code 
Currenly, nvgpu_runlist_cleanup_sw() includes a condition to check if
nvgpu_fifo struct in GPU structure is NULL. However, as nvgpu_fifo is
not included as a nvgpu_fifo pointer, it is not possible to set
nvgpu_fifo member as NULL. So, this patch deletes this condition.

Jira NVGPU-4817

Change-Id: I3484f74064450ad031bfa0beea9bbd1a49165f72
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279112
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Petlozu Pravareshwar
ee255ef8eb gpu: nvgpu: add unit tests for posix queue unit 
Add unit tests for posix queue unit.

Jira NVGPU-4478

Change-Id: I0a0e39be5e350d34c3546d177abfc523e174d607
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2275967
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 2020-12-15 14:10:29 -06:00
Petlozu Pravareshwar
cd7a3b3f0c gpu: nvgpu: unit: update fault injection handler 
Update fault injection handling for the following mock APIs:
 - NvRmMemMapGpuUserModeRegion()
 - NvRmMemUnmapGpuUserModeRegion()

JIRA NVGPU-2665

Change-Id: I6a9361cc37d3ceca247209302413a057321ff923
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2275067
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
50af902b71 gpu: nvgpu: unit: fifo: preempt-gv11b unit test 
This unit test covers all nvgpu.hal.fifo.preempt.gv11b module lines and
branches.

Jira NVGPU-4675

Change-Id: I5b7104c242e07fc61c4d155de3c0003b2bea7dfe
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2274044
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
87abec1ed9 gpu: nvgpu: pbdma_status in preempt poll 
gm20b_pbdma_handle_intr is only initializing pbdma_status
when either pbdma_intr_0 or pbdma_intr_1 is pending.
This could lead to using non-initialized chsw_status in
gv11b_fifo_preempt_poll_pbdma, and causing unexpected
failures in unit tests.

Read pbdma_status before checking for pbdma interrupts,
to make sure pbdma_status contains valid data.

Jira NVGPU-4887

Change-Id: If1bdb24ae04b58e85e4217c9c0854c01ca65525b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279111
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
5b47cd73fb gpu: nvgpu: fix misra 14.4 and 15.6 errors in vm.c 
Rule 14.4 requires if statement condition to be Boolean type. Rule 15.6
requires body of if statement should be a compound statement.
This patch fixes above rules in vm.c.

Jira NVGPU-4780

Change-Id: Iea605ab551a1cf232b59f7dda502df89899a3480
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2278607
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Scott Long
d0f3529d10 gpu: nvgpu: posix misra 12.1 fix 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from the
implementation of the is_power_of_2() macro.

Jira NVGPU-3178

Change-Id: I75117e9ab6e47beddebeebaa23c6408b6ceb88ad
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2278574
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Scott Long
5ee9a446b5 gpu: nvgpu: misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from various
common units.

Jira NVGPU-3178

Change-Id: I4b77238afdb929c81320efa93ac105f9e69af9cd
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277480
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Scott Long
a54c207c37 gpu: nvgpu: hal: misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from hal code.

Jira NVGPU-3178

Change-Id: If903544e1aa7264dc07f959a65ff666dfe89a230
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277478
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
ddaf1daae4 gpu: nvgpu: modify nvgpu_timeout_expired for UT 
In the current logic for nvgpu_timeout_expired(), function always
returns 0 if fault injection is enabled. This only helps for testing
timeout not expired scenarios. However, if nvgpu_timeout_expired() is
used in a while(true) loop, it is impossible to break the infinite loop.
This patch modifies nvgpu_timeout_expired() to not expire until fault
injection counter is non-zero. The function will now return -ETIMEDOUT
when fault injection is enabled and counter is zero.

Jira NVGPU-4675

Change-Id: I494031698ade19cf1ec5b75e4dbe5a1157da2aa7
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2275290
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
dadf9262d0 gpu: nvgpu: t23x: falcon init 
Add falcon s/w init for t23x igpu.

JIRA NVGPU-4383

Change-Id: Ia23d6a58b59ce5e6da0b96e20a39633a94ad8075
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2247226
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
17bcea0023 gpu: nvgpu: t23x: add TEGRA_234 chip id 
Add TEGRA_234 as supported tegra chip id and add nvgpu_next
platform data to supported platforms.

JIRA NVGPU-4383

Change-Id: I07eb88ca5a7f18516291066267ee41c002dc46bb
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2258722
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
d1e6b80a6f gpu: nvgpu: update common.gr intr unit test document. 
Update common.gr intr unit test document for missing api
functions being called from interrupt unit tests.

Jira NVGPU-4359

Change-Id: Ia5ea7f59c91c6d11616458708631d525dd9e91cb
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2278627
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 2020-12-15 14:10:29 -06:00
Philip Elcan
f2e2b29194 gpu: nvgpu: unit: add test for common.utils.string 
Add unit test for the common.utils.string unit.

JIRA NVGPU-4826

Change-Id: I4bfca346fb2202f9572199590f33a0461443fbc9
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2275456
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 2020-12-15 14:10:29 -06:00
Philip Elcan
0b0c4e6bd4 gpu: nvgpu: utils: fix typo in strnadd_u32 
Fix typo where the wrong value would be created because 'c' comes before
'd'.

JIRA NVGPU-4826

Change-Id: I7ad0a931187267951a470f5c02bc4c134cc9a498
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2275455
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
3ced484d3b gpu: nvgpu: unit: use BUG callbacks for EXPECT_BUG 
Use BUG() callback mechanism to implement EXPECT_BUG.
The longjmp is done in the callback.

Jira NVGPU-4512

Change-Id: I2544329ce5e8becb5bb9cc6df6cf50fe65eaf314
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2266394
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
1a3c1ee984 gpu: nvgpu: unit: add test for BUG() callbacks 
Add unit tests for the following functions:
- nvgpu_bug_register_cb
- nvgpu_bug_unregister_cb

Jira NVGPU-4512

Change-Id: I21a4bd55cfff080373b6234e517c1ee9cb51cb8a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2266392
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
1f3f34b906 gpu: nvgpu: add BUG() callbacks 
Add support for registering callbacks that will
be called on BUG().

Jira NVGPU-4512

Change-Id: I35c9b6c17db3b9fa5d098918223083f0b4aaace4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2266391
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 2020-12-15 14:10:29 -06:00
Petlozu Pravareshwar
569f34470e gpu: nvgpu: add Doxygen for posix queue 
Add Doxygen documentation for posix queue.

Jira NVGPU-4296

Change-Id: I21c310d1271c5a0802c64f7fe25223c50b86a7b9
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2275815
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Scott Long
20114c7c8c gpu: nvgpu: acr: misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from acr code.

Jira NVGPU-3178

Change-Id: Ibfcb23dbf9931efd1890c9b548c36462c55ae47d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277477
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
c96164ede4 gpu: nvgpu: remove unnecessary asserts in obj_ctx subunit 
Below functions in common.gr.obj_ctx subunit include unnecessary
asserts to ensure value is not truncated when parsing into U32 size.
nvgpu_gr_obj_ctx_gr_ctx_alloc()

Make use of nvgpu_safe_cast_u64_to_u32() and remove unnecessary
asserts

Jira NVGPU-4778

Change-Id: Ic06c2f4131b3bba35222f7de5441f82ecee6d83d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277158
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Scott Long
7444372237 gpu: nvgpu: static analysis misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from static_analysis.h.

Jira NVGPU-3178

Change-Id: Iae159038b5a99cbc98bd4de5c90b66b65e7f5b98
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2276790
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Abdul Salam
1481fe54e9 gpu: nvgpu: Remove dependency in FMON 
This patch removes dependency between pmu.clk and hal.clk.

Below is the implementation.
*Init the clk domains inside pmu.clk unit.
*Set this in a member variable and send it to hal.clk unit
*Use this to determine the valid clock domains and read the
 monitor registers for each valid domains.
*Return the domain with error code.
*With this all the clk domain data is removed from hal.clk and
 only pmu.clk uses it as it owns it.

JIRA NVGPU-4491

Change-Id: Ie57b2472cfaacfd2ce43ac7f95702bd95fb8bbaa
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2272416
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 2020-12-15 14:10:29 -06:00
vinodg
977cc73230 gpu: nvgpu: move wait_initialized to non-fusa section 
nvgpu_gr_wait_initialized function is being called from cg and
pg subunit and only be used as part of non-fusa code.
Add CONFIG_NVGPU_HAL_NON_FUSA checking for that function call.

Jira NVGPU-4676

Change-Id: Ibfdbe336a5e56bc5a2974576cffb9fb5cb5d2cc9
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: http://git-master.nvidia.com/r/c/linux-nvgpu/+/2276907
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
a126e00e28 gpu: nvgpu: compile out unused code in gr init unit 
Add CONFIG_NVGPU_GRAPHICS check before calling
g->gops>gr.init.preemption_state function.

Add NULL checking of pointer before deferecing those
pointers in de_init functions

Jira NVGPU-4676

Change-Id: Id9be0aebdcab4a8fb2b03e92e67c1c207b5b8eab
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: http://git-master.nvidia.com/r/c/linux-nvgpu/+/2276898
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Scott Long
d864904a49 gpu: nvgpu: mm: misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from mm code.

Jira NVGPU-3178

Change-Id: I51c53c3200530c8fb2b958d9d7d77b9366d9a202
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: http://git-master.nvidia.com/r/c/linux-nvgpu/+/2276837
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Scott Long
7378e16778 gpu: nvgpu: gr: misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from gr code.

Jira NVGPU-3178

Change-Id: I99a60f60f6edcc2acb7343c66d1c4c79752d4acb
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: http://git-master.nvidia.com/r/c/linux-nvgpu/+/2276774
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 2020-12-15 14:10:29 -06:00
ddutta
b7be2379c0 gpu: nvgpu: move nv-p2p outside nvgpu 
nv-p2p doesn't depend upon nvgpu directly
and hence it can be moved to nvidia repository.

Bug 200551105

Change-Id: Icd855ecdb91ede29f8b4d3631bb140092e7a8f7e
Signed-off-by: ddutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2275813
Reviewed-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Lakshmanan M
1c991a58af gpu: nvgpu: Add SM diversity support 
To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute on
different hardware resources. This feature proposes modifications
in the software to modify the virtual SM id to TPC mapping across
the mission and redundant contexts. The virtual SM identifier to TPC
mapping is done by nvgpu when setting up the patch context.

The recommendation for the redundant setting is to offset the
assignment by one TPC, and not by one GPC. This will ensure that both
GPC and TPC diversity. The SM and Quadrant diversity will happen
naturally. For kernels with few CTAs, the diversity is guaranteed
to be 100%. In case of completely random CTA allocation,
e.g. large number of CTAs in the waiting queue, the diversity is
1 - 1/#SM, or 87.5% for GV11B, 97.9% for TU104.

Added NvGpu CFLAGS to enable/disable the SM diversity support
"CONFIG_NVGPU_SM_DIVERSITY".

This support is only enabled on gv11b and tu104 QNX non safety build.

JIRA NVGPU-4685

Change-Id: I8e3eaa72d8cf7aff97f61e4c2abd10b2afe0fe8b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268026
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
031d2b77a2 gpu: nvgpu: remove log_common from fusa build 
Remove log_common.c from safety build since it is only used in
linux-specific code.

JIRA NVGPU-4818

Change-Id: Ic7f21617231cdc4f6a15a94d83275bcbe5901a30
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276025
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
b3960b2628 gpu: nvgpu: unit: improve gm20b channel coverage 
Add cases to trigger BUG() when passing invalid ch->chid.
This causes BUG() when computing register address for
ccsr_channel_inst_r(i) and ccsr_channel_r(i).

Jira NVGPU-4673

Change-Id: I313c6e6e65b38310af39f9817bb2398edf118d89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276022
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
b662fdfaf7 gpu: nvgpu: arch: add yaml support for nvgpu-next 
JIRA NVGPU-4383

Change-Id: Id6748f6e20e0ed831154a1d87639b03512bf049c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268327
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
seshendra
4ce4cdcd0f gpu: nvgpu: t23x: init hal for nvgpu-next 
Add hooks for nvgpu-next init hal.

JIRA NVGPU-4383

Change-Id: Ia899878743bca35d911c74444749f254ba94bbe0
Signed-off-by: seshendra <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243694
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
c7fa4109a8 gpu: nvgpu: remove extra semicolon in nvgpu_gr_config_init() 
Extra semicolon showed up as extra statement for which coverage was
missing as per Vectorcast. Remove the extra semicolon.

Jira NVGPU-4778

Change-Id: Id0135511a50d88c9a3ca5447dd6ebfd3dd9fa52d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276344
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
27d5dcc946 gpu: nvgpu: remove unnecessary asserts in global_ctx subunit 
Below functions in common.gr.global_ctx subunit include unnecessary
asserts to ensure value is not truncated when parsing into U32 size.
nvgpu_gr_global_ctx_init_local_golden_image()
nvgpu_gr_global_ctx_load_local_golden_image()

Make use of nvgpu_safe_cast_u64_to_u32() and remove unnecessary
asserts

Jira NVGPU-4778

Change-Id: Ia1da30f514632bca4a947a1018932a2424031e13
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2275919
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
9160bd29c3 gpu: nvgpu: gm20b: update whitelist reg list 
Added gm20b whitelist register access list with following
zcull registers:
gr_pri_gpcs_setup_debug_z_gamut_offset
gr_pri_gpcs_zcull_ctx_debug

Access to these registers is required by 3d API drivers to write
zcull depth values less than 0.25

Bug 2757650

Change-Id: I8eae7b027831b6c61b144898476dcb83cbe09644
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274559
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
6828487f70 gpu: nvgpu: unit: coverage for gm20b pbdma status 
Add coverage for the following function:
- gm20b_read_pbdma_status_info

Jira NVGPU-4673

Change-Id: I30c20932f84aac4a96efcb023ca85c5fbaecac1c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2270924
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
11aeb94d75 gpu: nvgpu: fix next_id in pbdma status 
populate_load_chsw_status_info and populate_switch_chsw_status_info
were using the wrong accessor to read next_id field from
pbdma status.

Use fifo_pbdma_status_next_id_v() to read next_id.
Also clean up code to use engine_status when available.

Jira NVGPU-4673

Change-Id: I9ec916dd6ce2f429ef24ebead47d315033b3f250
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2270923
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Nicolas Benech
cc7bffd8cd gpu: nvgpu: gops: name inner structures for doxygen 
When generating Doxygen XML, if an inner structure is anonymous, the
generated XML will remove the inner structure and merge its members
with the parent structure. This is not ideal for tooling, so this
patch adds a name to a few anonymous structures.

JIRA NVGPU-3510

Change-Id: I42556a6b2a2f9a156d9a74fa894197c845656adc
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274706
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
2088dc5d85 gpu: nvgpu: remove dead code for get gr runlist_id 
nvgpu_engine_get_gr_runlist_id gets the first instance of
active GR engine using nvgpu_engine_get_ids. Therefore the
engine_id is already known to be valid.
Remove call to nvgpu_engine_get_active_eng_info (which iterates
all engines), and fetch f->engine_info[engine_id] instead.
Also remove non-NULL test for engine_info, which could not
be true.

Jira NVGPU-4511

Change-Id: Ifcc0851e3d14d862e2ed7b21ea57f17a66eca9dd
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263617
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
ca17622b7e gpu: nvgpu: set invalid veid for non GR engines 
In nvgpu_engine_mmu_fault_id_to_eng_id_and_veid, set veid to
invalid for non-GR engines.

Jira NVGPU-4511

Change-Id: I2cec7898f8f7dec15224fdf70c444c0dd6de8a16
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262220
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
6fa5da61d7 gpu: nvgpu: use engine_id to access engine_info 
Generalize use of "engine_id" variable name to index f->engine_info.

Jira NVGPU-4511

Change-Id: Ie3bc2c701dc3bab833d6ac134273dd6a102528c2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262219
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:10:29 -06:00