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3041 Commits

Author SHA1 Message Date
Richard Zhao
c8d6a91de6 gpu: nvgpu: update .channel.enable/disable to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Ibd94ab8c9f0492bd6d20243525905d637eb8de66
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863438
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:56:04 -07:00
Richard Zhao
d9c8d317f0 gpu: nvgpu: update .read_state to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Ia5e30ebb0e8092b9cdc4c3f3cd524f585fd4b410
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863437
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:58 -07:00
Richard Zhao
2ff110f722 gpu: nvgpu: update .clear to use runlist_id and chid 
- Moving to use IDs rather than struct makes it reusable on server side.
- move channel bind/unbind to use .enable/.clear HALs

Jira GVSCI-15770

Change-Id: I86d4aae2953024e537e32a35fe9cabb1b91cd201
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863436
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:53 -07:00
Richard Zhao
3edae21ca6 gpu: nvgpu: vgpu: add vgpu-next cmds support 
vgpu-next cmds will be used if CONFIG_NVGPU_NEXT is set.

Jira GVSCI-15770

Change-Id: Iddb2c8b5c0ca412c99bfd01fd7d6411d4439131f
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863435
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-13 04:55:47 -07:00
Richard Zhao
7cd377568f gpu: nvgpu: vgpu: init ctx buffers for vf driver 
VF needs to allocate gr ctx buffers on gr init, since VF will manage the
gr ctx.

Jira GVSCI-15769

Change-Id: Ifd09e6b09306c0fd36bddc60caa3d0d56f2b29cb
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863434
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:35 -07:00
Austin Tajiri
6196d3f382 gpu: nvgpu: ga10b: fix missing gr registers 
Add the following missing GR registers/fields for GA10B:
 - gr_exception_fe_m
 - gr_exception_memfmt_m
 - gr_exception_pd_m
 - gr_exception_scc_m
 - gr_exception_ds_m
 - gr_exception_ssync_m
 - gr_exception_mme_m
 - gr_exception_sked_m
 - gr_fe_hww_esr_info_r
 - gr_mme_hww_esr_info_r
 - gr_sked_hww_esr_r
 - gr_sked_hww_esr_reset_active_f

Jira NVGPU-9217

Change-Id: I7bffb0f4e605ee09e75c7f550cece6779b71a80e
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2866781
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:16:01 -07:00
Richard Zhao
a23e574de0 gpu: nvgpu: vf: init syncpt mem 
Since gmmu map is moved to VF, the syncpt mem map is also on VF clients.

Jira GVSCI-15733

Change-Id: Iaf68070da860616f5301a822ce98581b8a1a6629
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863445
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:52 -07:00
Richard Zhao
a7d358f773 gpu: nvgpu: vf: init gmmu related structure 
vf driver implements gmmu map/unmap on client side.

- adds helper function to check whether nvgpu device is vf or legacy
vgpu.
- inits pd_cache struct for vf
- inits platform->phys_addr for ipa2pa

Jira GVSCI-15733

Change-Id: I46c84f0acdd167b9c4bdcec2f1c25f3acd6a0f71
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863430
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:47 -07:00
Richard Zhao
de0e1be1ed gpu: nvgpu: add g->func_regs 
rework nvgpu_func_* io accessors to use g->func_regs rather than use
g->regs. g->regs is invalid for VF.

Jira GVSCI-15732

Change-Id: I71e788ff135c5a286b273c151e1bd0a88e9d61e2
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863429
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:41 -07:00
Sagar Kamble
2acfb55780 gpu: nvgpu: fix tex rd coalesce disable logic 
NETLIST_REGIONID_SW_CTX_LOAD writes update gr_gpcs_tpcs_tex_m_dbg2_r to
default value that keeps rd coalesce enabled for LG & SU.

Disable rd coalesce for tex, lg and su after NETLIST_REGIONID_SW_CTX_LOAD
writes during gr init and golden ctx init for it to take effect.

For gr sw method handling, don't update the tex rd coalesce on interrupt
with offset *_SET_RD_COALESCE as we want to keep rd coalescing disabled.

Bug 3881919

Change-Id: Ie7e6616d48f84547ce3380bfa395910b7995c05b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857141
(cherry picked from commit b2c8827c65)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859538
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-07 22:46:44 -08:00
srajum
4ef14a13ff gpu: nvgpu: pmu use PWRCLK at fixed rate 204MHZ 
- On T234, Getting clock by calling clk.get_rate with CTRL_CLK_DOMAIN_PWRCLK
  domian which eventually pass clk index 1U which access TEGRA234_CLK_GPC0CLK.
- But GPC0 is floor-swept which returns makes clk.get_rate API fail
  (failed to query source clock).

Bug 3998230

Change-Id: I0a674b1856daf2b899827a7aafe0fc4185dd9964
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2862998
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-01 10:26:28 -08:00
Rajesh Devaraj
b754a2f0cf gpu: nvgpu: add and update falcon_dump_stats 
Add dump_falcon_info to avoid the duplication of entire
falcon_dump_stats function for new chips.

JIRA NVGPU-9216

Change-Id: I0a0c7b4655c625222a8fd3538d9e855568616e3a
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2858843
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-18 14:07:09 -08:00
Ramalingam C
d6be1bdcfe gpu: nvgpu: add is_pci_gpu 
Add a flag is_pci_gpu into platform data and gk20a, to support
igpu as pcie device.

JIRA NVGPU-9348

Change-Id: Iff1439ebb834b1673cb75ea26ca1e7626e1af0d5
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2835340
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-18 02:29:35 -08:00
Rajesh Devaraj
4bbc766454 gpu: nvgpu: add intr_0_pbcrc_pending gops for pbdma 
Add intr_0_pbcrc_pending hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: Ia08ce7761ac5b9a1af1166efbc1ecba97b54fc87
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857919
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-17 07:31:23 -08:00
Rajesh Devaraj
5aae7df6cd gpu: nvgpu: add reset_method pbdma gops 
Add reset_method hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: Ice9c3f6aea33a8dadae5841f1a6387303495ba98
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854547
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-17 07:26:24 -08:00
Richard Zhao
30727e8a93 gpu: nvgpu: remove golden_ctx_init_ch 
golden_ctx_init_ch is not used anmore because golden image creation has
been separated from channel/tsg.

Jira GVSCI-15771

Change-Id: I2af49717f8debbdb389ac64339e6ea7f84507a4e
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857563
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-16 00:00:59 -08:00
Richard Zhao
1e95ebef53 gpu: nvgpu: separate golden image creation from tsg/ch 
Golden image creation asks FECS to bind inst_block directly. It does not
need any setup on esched. Separating it from tsg/ch makes it for
flexible.

Jira GVSCI-15771

Change-Id: Id446371eb60b9520a7a284120a72c13d2215f4ea
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854096
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-16 00:00:53 -08:00
Rajesh Devaraj
cc17f80896 gpu: nvgpu: add gops to init pce2lce and grce configs 
This patch adds the following gops for CE unit:
- init_pce2lce_configs
- init_grce_configs

JIRA NVGPU-9329

Change-Id: I6e067b1f5066ccd71c4b287fa564a77afe4a25a5
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2856498
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-13 05:42:22 -08:00
Rajesh Devaraj
2e73de831f gpu: nvgpu: add is_sw_method_subch pbdma gops 
Add is_sw_method_subch hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: If18a2d510f77e269cb00dde609ec1c5941622858
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2855046
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-13 05:40:54 -08:00
rmylavarapu
e233ea5836 gpu: nvgpu: SWUD-lite updates for pmu unit. 
This is updating the pmu unit doxygen as per new guidlines.

Jira NVGPU-6976

Change-Id: Idfe43f32f457f0839e8bc5ad93e32fe7565d90b2
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2844654
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-31 19:28:15 -08:00
Rajesh Devaraj
77841cc9bb gpu: nvgpu: update pbdma_acquire intr handling 
To reduce duplication of pbdma_handle_intr_0_legacy to new chips, this
patch makes handle_intr_0_acquire as a HAL.

JIRA NVGPU-9325

Change-Id: I225318d45078367d09fc114202d9aeb0f1be374b
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2844872
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-24 03:38:01 -08:00
Austin Tajiri
6fffdddb7a gpu: nvgpu: add priv_ring.intr_retrigger HAL 
Add a priv_ring.intr_retrigger HAL for chips that need to
retrigger pending interrupts in the PRIV_RING ISR.

Jira NVGPU-9217

Change-Id: I976f26a39d148a0ce1ad54b53d982dc0af58197b
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839756
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-23 22:51:54 -08:00
Austin Tajiri
976b4efe64 gpu: nvgpu: add gops_gin HAL 
Add a gops_gin struct for handling chip-specific GIN functionality. For
now, it only has the get_intr_ctrl_msg HAL. Each per-unit INTR_CTRL
register holds an opaque 32-bit value that determines how an interrupt
is routed. The layout of this value is determined by GIN. This HAL
allows units to ask GIN how it should program their INTR_CTRL registers.

Jira NVGPU-9217

Change-Id: I18f86e09701634bdb39db6b6e4728cd3595caa02
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839755
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-23 22:51:47 -08:00
Rajesh Devaraj
4bb32e33e7 gpu: nvgpu: update pbdma_dump_intr_0 as an hal 
To reduce the duplication of HALs to new chips, this makes pbdma
dump_intr_0 as an HAL.

JIRA NVGPU-9325
JIRA NVGPU-9064

Change-Id: I737146068cb144165bae8666c04f876aed20a89c
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2847566
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-23 22:39:36 -08:00
Rajesh Devaraj
7ad50fee7c gpu: nvgpu: add new device types 
This patch adds macros for new device types based on the device
information table. Specifically, it adds the device type IDs for the
following engines:

- SEC
- NVENC
- NVDEC
- NVJPG
- OFA

Further, the max dev types has been updated as 57 in the device info
table. To support his, the corresponding macro has been updated as 58.

JIRA NVGPU-9501

Change-Id: I23f17c91da8a6063457c27763a62b1a08beeed0d
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2846203
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-21 16:52:39 -08:00
Rajesh Devaraj
afb971b66e gpu: nvgpu: update report_pbdma_error as hal 
To reduce the duplication pbdma_handle_intr_0 API to new chips, this
patch converts report_pbdma_error as a HAL.

JIRA NVGPU-9325

Change-Id: Ifcb0838037c750070c26343e008a176b26eebf16
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2845088
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-20 03:40:17 -08:00
prsethi
4dec633f5f gpu:nvgpu: clean the domain queues in abrupt close 
Domain queues are being cleaned as part of graceful close but does not
gets cleaned in case of abrupt app failures.
This change cleanup the queues for abrupt failures.

Bug 3884011

Change-Id: I8cd07b726718b1e13a05d4455a2670cedc9dee37
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2842632
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-17 01:40:36 -08:00
Divya
04cd344b35 gpu: nvgpu: free rpc_payload when driver is dying 
- During nvgpu module unload, the poweroff sequence
  will not wait for the ACK from the PMU for the RPCs sent.
- Due to this, rpc_payload struct info will be present
  in pmu seq struct.
- This can lead to memory corruption during unload path.
- To avoid this, return a different value for driver shutting
  down scenario from fw ack function and based on this return value
  free the RPC payload and release the respective pmu sequence struct.

Bug 3789998

Change-Id: I25104828d836ae37e127b40c88209da81754ffb8
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-13 06:10:52 -08:00
Rajesh Devaraj
3e2eff564f gpu: nvgpu: update pbdma intr enable set/clear masks as hals 
To reduce the entire duplication of pbdma_intr_enable for future chips,
make set and clear masks as HALs.

JIRA NVGPU-9325

Change-Id: Id8434fc15ca4bf542680a8452dc294f2c4068084
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2838036
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-09 20:04:11 -08:00
prsethi
8c710694e8 gpu:nvgpu: fix for consecutive domain submission 
When a user-domain gets removed, tsg belongs to this also gets removed
and runlist update happens accordingly. If same tsg was submitted to gpu
then updated runlist also needs to re-submit. This works fine with the
existing legacy cases but if GPU is running the shadow domain submitted
by manual mode scheduler and domain belongs to this gets removed then
updated runlist is not being submitted to GPU. This runlist buffer
inconsistency causes mmu fault later.

This change adds a "remove" field in the runlist domain which gets set
to true when runlist update happens for the channel removal. Later
worker thread submit the updated runlist if this flag set to true.

Bug 3884011

Change-Id: I3ce08a5a281e20661915746e70ac0dcd711f3f38
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2838808
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-09 12:26:12 -08:00
Rajesh Devaraj
2d3745810b gpu: nvgpu: add support flag for gsp stress test 
Add support flag for GSP stress test.

JIRA NVGPU-9347

Change-Id: I6b93e085b4e25798f1227297fd1baba8c1380604
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2833485
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-03 19:09:17 -08:00
Rajesh Devaraj
95c5d3d776 gpu: nvgpu: add flag to disable static pg 
This patch introduces the flag NVGPU_DISABLE_STATIC_POWERGATE. Further,
static pg related initialization APIs have been updated to check whether
this newly added flag is enabled. If this flag is enabled, then static
pg init gets skipped.

JIRA NVGPU-9350

Change-Id: I450b6dd2c541d31fc40fb5540e557b5db730fee2
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2834021
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-02 01:09:34 -08:00
Rajesh Devaraj
536ff1001e gpu: nvgpu: add flag to disable ecc stats 
This patch adds the flag NVGPU_DISABLE_ECC_STATS to disable the creation
of sysfs nodes that will be used to provide ECC counter values. Further,
this patch adds a check on whether NVGPU_DISABLE_ECC_STATS flag is
disabled before performing ECC sysfs initialization.

JIRA NVGPU-9349

Change-Id: I99bc3895d3a5ffcf73035351f55c63ed5c46356b
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2833907
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-02 01:09:13 -08:00
Alex Waterman
a9e21b487a nvgpu: Fixes for QNX build structure changes 
Minor updates in the path to header files.

Change-Id: I6fe1db8f050d9b168a1662f0cb65e15bc13c2195
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2810665
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-28 06:56:34 -08:00
vivekku
470c1738b5 gpu: nvgpu: gsp: host routed interrupt handling 
Changes:
- support for watchdog timer interrupt handling
- code modified to support gsp scheduler interrupts for ecc errors
directed to host
- interrupts like IMEM, DMEM, EMEM, Delayed Lock Step and incorrect
Register access

NVGPU-9273

Change-Id: I93a2ef0961aaa40e76ca7efe8450ce07a6709453
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2818202
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Tested-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-21 11:59:25 -08:00
rmylavarapu
7bbf10b04a gpu: nvgpu: gsp: bootstrap gsp scheduler firmware 
This change will call nvgpu_gsp_sched_bootstrap_hs which will bootstrap
the gsp with gsp scheduler firmware.

NVGPU-9297

Change-Id: If5de945dc7994666fd87ecf99e15ca2014c13573
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2826165
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-18 11:43:14 -08:00
Seeta Rama Raju
e0a9553533 gpu: nvgpu: Add magic value at instance block 
This is adding magic value in instance block while
initializing instance block for a context. This will
be verified by FECS firmware.

Bug 3638810

Change-Id: I7d304c1b622b3c9f50a7443e9fadce9bac869258
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2786274
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-17 02:21:07 -08:00
Tejal Kudav
31b2738f6a gpu: nvgpu: Add Epl Init 
EPL lib constructor is replaced by NvEplInit() by safety services.
NvGPU, being an EPL user, needs to call NvEplInit before using EPL
API to report errors.
NvEplInit() usage is limited to user space in Linux, so NvGPU is not
expected to call NvEplInit on Linux.

Bug 3863536

Change-Id: I7fc9b33d3443bd39a6367a0c691bddb80b9edb68
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2817245
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-15 20:55:54 -08:00
Atul Anand
5db14f3bfb nvgpu: Fix pm resource release sequence 
The memory leak issue was due to nvgpu_profiler_unbind_context() calling
nvgpu_profiler_pm_resource_release() for all resources which clears the
flag required by nvgpu_profiler_free_pma_stream() to release the memory
for perf_buf instance block.
Fixing this issue by splitting nvgpu_profiler_unbind_context() to release
all the pm resources at a later time separately.

Bug 3510455
Change-Id: Ibab8d071693e600c46f7e7f16575e36e6f62af3c
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2825013
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-15 15:13:29 -08:00
mpoojary
9b73378362 gpu: nvgpu: Add support for loading ctxsw encrypted binaries 
Add checks to load encrypted CTXSW binaries for T234,
when executing in silicon; else load the non encrypted
binaries.

Jira NVGPU-9303

Change-Id: Icf55ed76b1a7340006b00d1c24472d26462a880c
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2819642
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Dinesh Kamalakannan <dineshka@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
 2022-12-14 23:48:10 -08:00
Dinesh T
2509287e71 gpu: nvgpu: enable NVGPU on OOT 
This patch is required for
 - enabling NVGPU driver on OOT by enabling various
   configs required.
 - replacing new APIs for some deprecated APIs by
   guarding with linux version for soc.c.
 - CONFIG_TEGRA_HV_MANAGER is enabled by default in OOT kernel,
   removing CONFIG_TEGRA_HV_MANAGER check from various places.

Bug 3812973

Change-Id: I07f0b738ca95d4a3996e7f3ee5e895463db0626b
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822434
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-13 16:56:58 -08:00
vivekku
a92bca9772 gpu: nvgpu: gsp: created cmd for GSP to bind ctx reg 
Changes
- create command for GSP firmware to bind ctx register.

NVGPU-8730

Change-Id: If92bbbc0169b6466e55f3dff05828b2b649ad3de
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2815472
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-13 06:22:02 -08:00
rmylavarapu
01eb416745 gpu: nvgpu: gsp sched: enable gsp sw init for safety build 
Changes
1. Remove dGPU flag dependency on calling gsp sw init on tot.
2. Created Enable flag for gsp scheduler to enable them on ga10b
platforms.
3. Engine config flag is only enabled for dGPU enabled platforms, as gsp
is using engine functions it need to be enabled for all gsp sched
enabled builds.
4. Changes in gsp_sequence_init/de_init where on qnx we are seeing
issues.

NVGPU-9297

Change-Id: Ia4bce85ae8fd2794da1553e9ea418c76845a10ac
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822537
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-12 06:06:09 -08:00
rmylavarapu
398a30a546 gpu: nvgpu: gsp sched: get the binary file names as per debug fuse 
Changes
 1. Created gsp hal function to read the hardware config register
    to tell whether the board is debug fused.
 2. Created function to get the binary file names as per debug fuse.

NVGPU-9295
Bug 3897331

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: Ia8462aa6f3d8d0d538c06f35245c965e106b3d37
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822443
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-11 19:09:29 -08:00
prsethi
b4494a4b86 gpu:nvgpu: fix the nvs mmap issues 
- As part of mmap call handler mmap_sem is being acquired which is
causing an BUG: scheduling while atomic:. This is happening because
mmap callback gets called with mmap_sem held. The mmap file handler
is called via call_mmap() via mmap_region() via do_mmap(), and the
caller of do_mmap() must hold down_write(&current->mm->mmap_sem).
To fix this issue removing the mmap_sem locking from nvs mmap handler.

- If remap_vmalloc_range() is used to map the pages to userspace then
allocated pages should be mapped into virtually contiguous space by
passing VM_USERMAP flag to vmap(). Passing VM_USERMAP to vmap() call
if API nvgpu_dma_alloc_flags_sys() is called with flag
NVGPU_DMA_VM_USERMAP_ADDRESS.

Bug 3884011

Change-Id: I64264f6f6e0dd75b1f828dc58355d740e6ef5ccb
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2820781
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-09 15:19:07 -08:00
Dinesh T
373398a46b gpu: nvgpu: Add os specific call to initialize the channels 
Add OS specific function to return the number of syncpoints
available to the GPU. This is required for making the
syncpoints as configurable.

Linux: The default number of syncpoints is 512.

Bug 3644504

Change-Id: Iddbc38cb25480876d6d8f39f039218a1b2b22605
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2820152
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-06 04:47:24 -08:00
Debarshi Dutta
8e60795b9c gpu: nvgpu: Add correct nomenclature for NVS ioctls 
Its preferable to use the following naming convention
NVGPU_<group>_IOCTL_<function>.

The IOCTL interfaces are updated accordingly.

Also, all KMD based defines as part of the UAPI need
to be prefixed by NVGPU.

Jira NVGPU-8619

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I2210336536cbcc0415885f3f92a2f7fa982fa39c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2814484
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-06 04:40:05 -08:00
Debarshi Dutta
2d38294912 gpu: nvgpu: add Doxygen documentation for Control-Fifo 
Add Doxygen for Control-FIFO APIs. Add null checks where
necessary.

Jira NVGPU-8619

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I75f92108c73a521e45299b8870e106916954e7a8
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2805551
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Tested-by: Prateek Sethi <prsethi@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-29 04:06:53 -08:00
Shashank Singh
7abaeda619 gpu: nvgpu: add API to query page table memhandles 
Add API to query all memhandles used for pde and pte.
- Some direct pde/pte allocation should also add entry to the pd-cache
full list.
- Add OS API for querying MemServ handle from nvgpu_mem.
- Traverse through all pd-cache partial and full lists to get memhandles
for all pde/pte buffers.

Jira NVGPU-8284

Change-Id: I8e7adf1be1409264d24e17501eb7c32a81950728
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2735657
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-24 11:19:10 -08:00
Debarshi Dutta
63e8de5106 gpu: nvgpu: Remove NVGPU_SUPPORT_NVS_CTRL_FIFO 
Now that we are planning to enable CTRL_FIFO support with NVS,
there is no need for a separate enabled flag for the same.

CTRL_FIFO support is instead determined by the presence of
NVGPU_SUPPORT_NVS enable flag alone.

For non-auto platforms, Control-Fifo can be disabled by restricting
access to /dev/nvsched_ctrl_fifo.

Jira NVGPU-8619

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I9dbec60e5668f38e1460c43800584e88b16a2550
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2814435
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-11-24 00:47:37 -08:00