This CL covers the following implementation,
1) Power Sensor Table parsing.
2) Power Topology Table parsing.
3) Add debugfs interface to get the current power(mW), current(mA) and
voltage(uV) information from PMU.
4) Power Policy Table Parsing
5) Implement PMU boardobj interface for pmgr module.
6) Over current protection.
JIRA DNVGPU-47
Change-Id: I7b1eefacc4f0a9824ab94ec8dcebefe81b7660d3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1217189
(cherry picked from commit ecd0b16316cb4110118c6677f5f03e02921c29b6)
Reviewed-on: http://git-master/r/1241953
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
JIRA DNVGPU-123
now a function can be called with GPC2CLK value
It will take care calculating slave clock values
and calling VF inject to program clock
Made programming of boot clock code to use this
newly created function.
Change-Id: I74de7e9d98e379e94175ed2d9745ce3ab6c70691
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1221976
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1235056
JIRA DNVGPU-123
Function will copy possible clock points for
a given master clock domain to pointer passed.
pointer with NULL value and count of zero can be passed
to query number of clock points for a given domain so that
memory can be allocated and function called again to
fill clock points
Change-Id: Iec6206f23789980036be99793599e934bd221035
Reviewed-on: http://git-master/r/1218912
(cherry picked from commit 9219697bff1e12deb605325055a02a7b387996e9)
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1235055
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
JIRA DNVGPU-123
function was added to retrieve V for F or
F for V for a given clock domain.
Clock domain can be master or slave.
F or V can be intermediate point between two
successive V or F values in VF table.
VF table should be cached before calling this function.
A F value below Fmin will return Vmin.
F > Fmax will return error
A V value above Vmax wil return F max.
A V value below Vmin will return error.
Change-Id: I28b4e8647510c6933e9e1204cfff31d74616e11a
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1211234
(cherry-picked from commit 5b83b03f2454fbec8d49a064ed09b09c92d3e9fa)
Reviewed-on: http://git-master/r/1235054
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
We need to wait for scrubber to have finished before we can allow
any accesses to memory. Do the wait in place where on iGPU we would
do FB reset.
Bug 1799537
Bug 1815139
Change-Id: Ic92dee936388a13c4abf0b295fd99581522c430f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1235541
(cherry picked from commit 1ef73ecb4e37da042e7117426ab2823b7f4528dc)
Reviewed-on: http://git-master/r/1239955
GVS: Gerrit_Virtual_Submit
bug 200088648
sparse warning reported that the function was not
defined. This was due to a missing include
Change-Id: Ia6153a2f3348a86e78add95bcfff998505b47cdd
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1237845
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Implement the basic code to swap between PCIe bus speeds for the GPU.
Other GPUs are not supported yet. Currently the following speeds can
be used:
Gen1 (2.5 MTPS)
Gen2 (5.0 MTPS)
gp106 on DPX2 does not support Gen3.
JIRA DNVGPU-89
Change-Id: I8bebfc9d99b682bdcff406fa56e806097dd51499
Reviewed-on: http://git-master/r/1218177
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1227925
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
The lowest page table level may hold very few entries for mappings of
large pages, but a new page is allocated for each list of entries at the
lowest level, wasting memory and performance. Compact these so that the
new "allocation" of ptes is appended at the end of the previous
allocation, if there is space.
Bug 1736604
Change-Id: I4c7c4cad9019de202325750aee6034076e7e61c2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1222810
(cherry picked from commit 97303ecc946c17150496486a2f52bd481311dbf7)
Reviewed-on: http://git-master/r/1234995
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Suppress error message when nvgpu tries to load VBIOS overlay, but
one is not found. This situation is normal. This is done by moving
gk20a_request_firmware() to be nvgpu generic function
nvgpu_request_firmware(), and adding a NO_WARN flag to
it.
Introduce also a NO_SOC flag to suppress attempt to load firmware
from SoC specific directory in addition to the chip specific
directory. Use it for dGPU firmware files.
Bug 200236777
Change-Id: I4666bee512ae0914ef92b75f068685cb2b503cc8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1223839
(cherry picked from commit e9ae74dfbde3c3d2b103e1927aa92ec7d97cd76d)
Reviewed-on: http://git-master/r/1233412
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Use entry->mem for determining the target aperture bits of the memory
block represented by entry->mem in update_gmmu_pde0_locked(), instead of
pte->mem that holds the parent memory where this bit is written to.
Previously this has worked because all page tables have been in the same
aperture, but really large userspace allocations may push a part of them
suddendly to sysmem.
Bug 1809939
Change-Id: I3372487c6ae9793018ce44552ded3fb1ba4d145a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1218636
(cherry picked from commit a92596f6e8e621e51b6afae9ab7e62044d6311eb)
Reviewed-on: http://git-master/r/1220525
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
For bar2 and pmu instance blocks, use gk20a_aperture_mask()
to select target address (i.e. if address is in sysmem or
vidmem) based on aperture
Also add target accessors for gr_fecs_new_ctx and
gr_fecs_arb_ctx_ptr
Jira DNVGPU-22
Change-Id: Ieaa80bd83a4191fe57b7fba6e0f9cdaeb195a077
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1216138
(cherry picked from commit 7a9f4175abc5dddf0879215de4637b7b6eb0ab7b)
Reviewed-on: http://git-master/r/1219712
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
We are using gp10b prod values for gp106, and they are incompatible.
Because of this we are accessing invalid registers.
Delete all prod vals for gp106 until we have generated new ones.
Bug 1799537
Change-Id: Id805e933bd19f6ccaf28274cd69140f9f93cd4ea
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208716
(cherry picked from commit 50d3ecfbfa42795d5eaa20c977cf83613498a804)
Reviewed-on: http://git-master/r/1217287
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add support for cyclestats snapshots in the virtual case
Bug 1700143
JIRA EVLR-278
Change-Id: I353efac6a17704c815a99745ac04d2c3d831351b
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1216644
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Since page tables could either reside either in sysmem
or vidmem, use gk20a_mem_get_base_addr() to get the
base address for buffer
This API will take care of returning proper base address
Jira DNVGPU-20
Change-Id: I3422b51c3ffb8fb86f1dc5095263fc8f19dae44d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1206407
(cherry picked from commit 3c4b22c35b2c4eec33234c2f8dccd9de9422d093)
Reviewed-on: http://git-master/r/1210962
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Event notifications on TSGs should only be sent to the channel that caused the
event to happen in the first place, not evey channel in the tsg. Any more and
the debugger will not be able to tell what channel actually got the event.
Worse yet, if all the channels in a tsg are bound to the same debug session
(as is the case with cuda-gdb), then multiple nvgpu events for the same gpu
event will be triggered, causing events to be buffered and the client to get
out of sync.
One gpu exception, one nvgpu event per tsg.
Bug 1793988
Change-Id: Iee36c774f193554ffb9ab7c1650ee0610e476a99
Signed-off-by: Cory Perry <cperry@nvidia.com>
Reviewed-on: http://git-master/r/1194206
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Unknown engine is expected, as we do not support all dGPU engines.
Remove the error spew.
JIRA DNVGPU-26
Change-Id: I3d43253b8cab4e51b426536e4899a62156d0da16
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1206465
(cherry picked from commit a3fa13f6be4ff60e90558326474af3d1b315aa43)
Reviewed-on: http://git-master/r/1208408
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Added preemption mode (WFI, GFXP, CTA and CILP) support for gp10x
family gr class (PASCAL_B and PASCAL_COMPUTE_B).
Bug 200221149
Change-Id: Ia8b781c5baedba660db5997f190a0b363286ed7f
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1193209
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
