We right now compare requested value to the last
freq value. Last freq value is always a rounded
value, whereas requested value need not be a
rounded value
Hence it is incorrect to compare requested value
to last freq value
Fix this by comparing rounded value to last_freq
Change-Id: I7c6ea7c4e57105598c9af75efe70016b7fa8038b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1287360
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
The soc tegra headers are unified and moved all the content of
linux/tegra-soc.h to the soc/tegra/chip-id.h to have the
single soc header for Tegra.
Change-Id: I281e19dd3eb1538b8dfbea4eb0779fb64d1fcffa
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1288365
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
bug 200269171
Updating PMU firmware to fix voltage raise when switching mclk to 810mhz
with CLFC and MSCG enabled. The fix is to make sure that clock domain is
not evaluated in CLFC if MSCG has engaged anytime after the previous
evaluation
Change-Id: I2b6979ed3361f47273f2643c27c005deac49dc8b
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1286437
(cherry picked from commit dbfccb42614ec9361628b3c3427a65d3fe908597)
Reviewed-on: http://git-master/r/1287461
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
The recently added refcount tracking support had a slight mishap in
refactoring some printks. Fix a typo to make the support compile again
when enabled.
Bug 1826754
Change-Id: Ifd76d644932fa219751db82a0beb3c8482ea68c3
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1285922
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Use the timers API in the gk20a code instead of Linux specific
API calls.
This also changes the behavior of several functions to wait for
the full timeout for each operation that can timeout. Previously
the timeout was shared across each operation.
Bug 1799159
Change-Id: I2bbed54630667b2b879b56a63a853266afc1e5d8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1273826
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Hold debug_s->ioctl_lock for all debug session
IOCTLs to prevent multi-threaded user space
IOCTL calls
debug session IOCTL calls are not thread-safe
and hence this serialization is required
Bug 1832267
Change-Id: I847ac951601d4f0093546b592bdb8c8f00185317
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1286436
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
In gk20a_pm_shutdown(), we currently do not wait
for IOCTLs or threads in progress and directly
proceed with shutdown sequence
This can cause random hangs during system shutdown
Fix this by calling gk20a_wait_for_idle() after
we disable runtime PM in gk20a_pm_shutdown()
Bug 200260926
Change-Id: I0f06ba9232263fcb09c6e9d246be89deec053d44
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1286522
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
- Added HAL support to get current
pstate from clk_arb
Note - This function is inherently unsafe to call while
arbiter is running arbiter must be blocked
before calling this function
JIRA DNVGPU-165
Change-Id: I4e9f5eba7739280bddd9ee661fd314288c129516
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1286378
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
- with help of WRITE_ONCE() & ACCESS_ONCE()
make sure variable pmu->mscg_stat read/write goes through
without optimization
- Added WRITE_ONCE() define for kernel-3.18 version & below
to support backward compatibility
issue: inconsistencies on getting MSCG to trigger consistently in P5
due to a lack of memory barrier around and volatile accesses to the
variable pmu->mscg_stat
JIRA DNVGPU-71
Change-Id: I04d30493d42c52710304dbdfb9cb4a1e9a76f2c0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252524
(cherry picked from commit 8af7fc68e7ab06a856ba4ef4e44de7336682361b)
Reviewed-on: http://git-master/r/1271614
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Print process name if we fail submit due to gk20a_busy()
failure
This is helpful in debugging and to know the process name
submitting jobs to nvgpu after system shutdown was
already triggered
Bug 200262275
Change-Id: I34d8c07fc96fd5556afa982bfd56f7f3964449d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1284113
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
When gpu host is executing a context, there should not be any calls
to fecs that can change the current context in execution. For some
reason legacy fmodels are calling fecs method to golden
context restore while loading golden context for new channel.
This call is not required and should not be called. Only first
time during golden context creation, fecs methods like bind can be
called and it is pretty safe to do.
Bug 1834201
Change-Id: Ia6178e875e3ac37fb1cf10e27976c26b9a02c56f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1284512
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Setting timeslice for virtualized case was not effective,
because both ioctls NVGPU_TSG_IOCTL_SET_TIMESLICE and
NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE were calling the
native function to set TSG timeslice.
- Fixed wrapper function to call HAL
- Defined HAL function for "native" set TSG timeslice
- Also, properly update timeout_us in TSG context, in
virtualized case.
This change also moves the min/max bounds checking for
tsg timeslice into the native function implementation.
There is no sysfs node for these parameters for vgpu,
as RM server is ultimately responsible for this check.
Bug 200263575
Change-Id: Ibceab9427561ad58ec28abfff0c96ca8f592bdb9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1283180
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
The timeslice values that can be selected for a particular channel/tsg
are bounded by a static min/max. This change introduces two sysfs
nodes that allow these bounds to be configured from userspace.
min_timeslice_us
max_timeslice_us
Bug 200251974
Bug 1854791
Change-Id: I5d5a14225eee4090e418c7e43629324114f60768
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1280372
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
When kernel adds patches to a context, kernel needs to update
the patch count in order for FECS to pick up the new patches.
Previously patching was done only at the context creation
time. Now patching is used also when changing preemption mode,
but the patches did not take effect due to not updating count.
Update patch count every time we end patching of a context.
Bug 1852094
Change-Id: Ic2150741609d1d1956769e439ce1c5f2edcacb84
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1280424
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reorganize the HW headers of gk20a. The headers are moved to a
new directory:
include/nvgpu/hw/gk20a
And from the code are included like so:
#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
This is the first step in reorganizing all of the HW headers for
gm20b, gm206, etc. This is part of a larger effort to re-structure
and make the driver more readable and scalable.
Bug 1799159
Change-Id: Ic151155cbc2e6f75009f2d9d597b364a1bed2c4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1244790
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
If enabled, track actions (gets and puts) on channel reference counters.
Dump the most recent actions to syslog when
gk20a_wait_until_counter_is_N gets stuck when closing a channel.
GK20A_CHANNEL_REFCOUNT_TRACKING specifies the size of the action
history. Default is to disable completely, as this has some runtime
overhead.
Bug 1826754
Change-Id: I880b0efe8881044d02ae224c243a51cb6c2db8c1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1262424
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
- Added struct pmu_pg_stats_data to extract
data from multiple version of pmu pg statistics
- Added pmu_pg_stats_v2 interface to fetch
PG statistics data from PMU
- Added MSCG debugfs node to read mscg
statistics from PMU.
- Added pmu_elpg_statistics HAL support for
gp106 PG statistics read.
- Made changes to gp104/gp106
pmu_elpg_statistics HAL to support
for struct pmu_pg_stats_data
JIRA DNVGPU-165
Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252798
(cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd)
Reviewed-on: http://git-master/r/1271615
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Kickoff latencies when GPFIFO is in vidmem grow significantly as
function of number of GPFIFO entries. Move GPFIFO to sysmem to
improve kickoff latency.
Bug 1848369
Change-Id: Ie95d10df26b4f1370f7250a8fbf0f7ef0211df32
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit 897cb579a759bbe8455ce368413979e91eb0d475)
Reviewed-on: http://git-master/r/1281564
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move the GPU allocators to common/mm/ since the allocators are common
code across all GPUs. Also rename the allocator code to move away from
gk20a_ prefixed structs and functions.
This caused one issue with the nvgpu_alloc() and nvgpu_free() functions.
There was a function for allocating either with kmalloc() or vmalloc()
depending on the size of the allocation. Those have now been renamed to
nvgpu_kalloc() and nvgpu_kfree().
Bug 1799159
Change-Id: Iddda92c013612bcb209847084ec85b8953002fa5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1274400
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
In gk20a_busy() we check if dev is NULL and return -ENODEV if so. But
before that we've already dereferenced dev by passing it to
get_gk20a(). Defer call to get_gk20a() until after the NULL check.
Bug 200192125
Change-Id: I943a9e96d13ff8cb4333fe20a941c8e95d159a66
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1280349
GVS: Gerrit_Virtual_Submit
Add a platform flag and logic to disable ASPM on boot if a
platform does not want ASPM enabled.
Bug 200256272
Change-Id: I378997290377ef8ffa21bf8e7f3f59fa134b3d4d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1263271
(cherry picked from commit 01e4700b74f4b4c6f0b9ffb40747653f2b63ea3c)
Reviewed-on: http://git-master/r/1274477
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Handle possible asynchronous GPU driver shutdown more gracefully.
This occurs when the GPU disappears from the PCI bus, for example,
if it overheats or detects an over current event.
Also add a preprocessor check to make sure that the
gk20a_channel_cancel_pending_sema_waits()
is always defined. In some builds CONFIG_SYNC is disabled but the
gk20a_remove_support() code does not check for this.
Bug 1816516
Bug 1807277
Change-Id: I932e312291c5c6a6ac5e13525ce8ca56a1be3652
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250028
(cherry picked from commit 337810f8c478238a38d8553c1492622d5fa9aafa)
Reviewed-on: http://git-master/r/1274476
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Move the code that waits for deferred interrupts to nvgpu_common.c and
make it global. Also rename that function to use nvgpu_ as the function
prefix.
Bug 1816516
Bug 1807277
Change-Id: I42c4982ea853af5489051534219bfe8b253c2784
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250027
(cherry picked from commit cb6fb03e20b08e5c3606ae8a5a9c237bfdf9e7da)
Reviewed-on: http://git-master/r/1274475
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Fix miscellaneous issues seen during driver shutdown.
o Make sure pointers are valid before accessing them.
o Busy the GPU during channel timeout.
o Cancel delayed work on channels.
o Avoid access to channels that may have been freed.
Bug 1816516
Bug 1807277
Change-Id: I62df40373fdfb1c4a011364e8c435176a08a7a96
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250026
(cherry picked from commit 64a95fc96c8ef7c5af9c53c4bb3402626e0d2f60)
Reviewed-on: http://git-master/r/1274474
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
In many helper functions like gk20a_readl() the code assumed that
the GPU is present and registers and available. However, during
GPU shutdown this may not be the case.
In theory the driver should not be accessing GPU registers during
GPU shutdown (since shutdown is triggered by GPU registers being
unavailable) but these changes handle any missed cases where this
may happen.
This goes for GPU device access as well. Many parts of the code
assume that if the struct gk20a is valid, the the GPU dev must be
there are well. This isn't always the case, it seems.
Bug 1816516
Bug 1807277
Change-Id: Icaf6fd56ab7860724e77bda0f5e8d48f0da15642
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250024
(cherry picked from commit e8c9997b2d7cd424d798ecfce1307e6193c0cf32)
Reviewed-on: http://git-master/r/1274473
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Enable FECS ctxsw tracing for gp106. Ensure that FECS records
have been written to memory before accessing the ring. Update
read index only once all records have been processed.
Jira EVLR-424
Change-Id: I1a21f841fcce1588397408906d77e2c3bf4a8c01
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1258243
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
We use GPU reference clock as a divider. Check before division that
reference clock is not zero.
Change-Id: Ie453a78b422b2e740daeb7c12ce5b06faa52ba76
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275743
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
In gk20a_submit_prepare_syncs(), after we have allocated wait_cmd
we check the results. If we failed to allocate wait_cmd, we still
jump to the error label that tries to free wait_cmd.
Create an own error labal for allocation before wait_cmd, and use
that if we fail to allocate wait_cmd.
Similarly create an error label for incr_cmd, and use that only once
incr_cmd has actually been allocated.
Change-Id: I1f8bc1d947c524038f5f237358a5e6b0dc2e6ac3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275742
GVS: Gerrit_Virtual_Submit
When allocating job channel_gk20a_job structure we assign the result
of allocation to *job_out, but we check the result of allocation
in job_out.
Change the check to check for result in *job_out.
Change-Id: Ia170cfa2dd5730665434b4c223c5a2f9502c744d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275741
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
We use &ch->error_notifier_mutex to protect
writes and free of error notifier
But we currently do not protect reading of
notifier in gk20a_fifo_set_ctx_mmu_error()
and vgpu_fifo_set_ctx_mmu_error()
Add new API gk20a_set_error_notifier_locked()
which is same as gk20a_set_error_notifier()
but without the locks.
In *_fifo_set_ctx_mmu_error() APIs, acquire
the mutex explicitly, and then use this new
API
gk20a_set_error_notifier() will now just call
gk20a_set_error_notifier_locked() within
a mutex
Bug 1824788
Bug 1844312
Change-Id: I1f3831dc63fe1daa761b2e17e4de3c155f505d6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1273471
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Process long regops lists in 4-kB fragments, overcoming the overly
low limit of 128 reg ops per IOCTL call. Bump the list limit to 1024
and report the limit in GPU characteristics.
Bug 200248726
Change-Id: I3ad49139409f32aea8b1226d6562e88edccc8053
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/1253716
(cherry picked from commit 22314619b28f52610cb8769cd4c3f9eb01904eab)
Reviewed-on: http://git-master/r/1266652
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
- PG statistics read support for multiple engines
- updated stat_dmem_offset member to array to hold
dmem offset of PG engines
- PMU allocates memory in DMEM for each PG engine requested,
updated gk20a_pmu_get_elpg_residency_gating() to get
engine statistics for requested PG engine
JIRA DNVGPU-71
Change-Id: I2ddade37f85716f757bf33034dbff816184577eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1250506
(cherry picked from commit 68ba7a97d6662b87d0e489365d8afb8e2d237a03)
Reviewed-on: http://git-master/r/1270972
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
