Do not call PMU ELPG calls if ELPG should be disabled. Also skips
initialization of PMU ucode if PMU is disabled.
Bug 1567274
Change-Id: Ia9cd3b553c358142ee05a1b0e0832f9412f7cf17
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/593335
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Fix below sparse warnings :
warning: Using plain integer as NULL pointer
warning: symbol <variable/funcion> was not declared. Should it be static?
warning: Initializer entry defined twice
Also, remove dead functions
Bug 1573254
Change-Id: I29d71ecc01c841233cf6b26c9088ca8874773469
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/593363
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
With CG enabled sometimes fifo could not be idled
during firmware load.
Bug 200042729
Change-Id: I43d7551c0c7c19314c52ac5f678afed8c6df6415
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/559077
Reviewed-by: Automatic_Commit_Validation_User
Convert GR and LTC HALs to use const structs, and initialize them
with macros.
Bug 1567274
Change-Id: Ia3f24a5eccb27578d9cba69755f636818d11275c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590371
When initializing fifo, we ignore several error conditions. Add
checks for them.
Change-Id: Id67f3ea51e3d4444b61a3be19553a5541b1d1e3a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553269
If engine status is in context switch in the fifo mmu fault handler,
dump falcon stats and gr stats for each engine.
Bug 1544766
Change-Id: Idfa9772b7e67072941144ac3bdd73e791fdc2b23
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/553205
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
To help remove the nvhost dependency from nvgpu, rename ioctl defines
and structures used by nvgpu such that nvhost is replaced by nvgpu.
Duplicate some structures as needed.
Update header guards and such accordingly.
Change-Id: Ifc3a867713072bae70256502735583ab38381877
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542620
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Retrieve channel count from gm20b specific header instead of the
gk20a header. This increases channel count from 128 to 512.
Change-Id: I96d4887432852795f7f526e33f0d3d2458f3af0e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500623
Invalid method needs to be cleared in gm20b to prevent getting same
interrupt again.
Change-Id: I4d83d1a27e5c711b5d82b95552be84d5f16a13e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500286
Runlist event is not sent in gm20b for updated runlist. Polling is
the preferred way also for gk20a.
Bug 1555239
Change-Id: I60de084db69f848f63451f1f3078f183ca51ba50
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500241
Use TSG specific API gk20a_fifo_recover_tsg() in following cases :
- IOCTL_CHANNEL_FORCE_RESET
to force reset a channel in TSG, reset all the channels
- handle pbdma intr
while resetting in case of pbdma intr, if channel is part of
TSG, recover entire TSG
- TSG preempt failure
when TSG preempt times out, use TSG recover API
Use preempt_tsg() API to preempt if channel is part of TSG
Add below two generic APIs which will take care of preempting/
recovering either of channel or TSG as required
gk20a_fifo_preempt()
gk20a_fifo_force_reset_ch()
Bug 1470692
Change-Id: I8d46e252af79136be85a9a2accf8b51bd924ca8c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/497875
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
- add support to handle MMU faults on a channel in TSG
- first get the ID and type of channel that engine is running
- if TSG, abort each channel in it
- if regular channel, abort that channel
- also, add two versions of API set_ctx_mmu_error(), one for
regular channel and another for TSG
Bug 1470692
Change-Id: Ia7b01b81739598459702ed172180adb00e345eba
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/497874
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
- add and export API "gk20a_fifo_recover_tsg()" to
recover a TSG
- if TSG is running on any engine, then trigger MMU fault
on those engines
- otherwise, abort each channel in TSG
- modify channel specific API engines_on_ch() to generic
engines_on_id() which will take an ID and a flag to specify
whether ID is for channel or TSG and return engines running
on that ID
- modify channel specific API get_faulty_channel() to generic
get_faulty_id_type() which will take pointers to ID and type
of ID (either a regular channel or TSG)
- remove runlist update from recover_ch() since
no need to touch runlist during recovery
- set error notifier first and then only abort the channels
for TSG recovery path
- also, add necessary accessors to get engine
status type as TSG
Bug 1470692
Change-Id: I7137f611f80916b3d256d4b0dc6e5cf1e93eef6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/497873
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
If a channel is already scheduled as regular channel, we should not
allow it to be marked as TSG since it will fail book keeping of
number of active channels in a TSG
This way we can force to bind the channels first and then only
make them active
Also, remove duplicate function declaration added during branch merge
and one unnecessary comparison with zero
Bug 1470692
Change-Id: I88f9678919e4b76de472c6dda21e4537520241c4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/497903
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add API gk20a_fifo_preempt_tsg() which takes ID of tsg
and preempts it
Bug 1514064
Bug 1470692
Change-Id: I1d52c1dd7a9aecc1314b0f223fe4eedecc033629
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/495583
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Regenerate clock gating lists. Add new blocks, and takes them into
use. Also moves some clock gating settings to be applied at the
earliest possible moment right after reset.
Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/457698
The nvgpu driver now supports using the Tegra graphics virtualization
interfaces to support gk20a in a virtualized environment.
Bug 1509608
Change-Id: I6ede15ee7bf0b0ad8a13e8eb5f557c3516ead676
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/440122
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
PBDMA timeout can cause stale data in FIFO. Default value equals 1ms.
Increase it to max.
Bug 1537636
Change-Id: I1c6c6b10abaece3a64b77b9b3ef77ff726ff67cf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/457047
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Chang <allchang@nvidia.com>
Tested-by: Allen Chang <allchang@nvidia.com>
In runlist we first write channel count in TSG entry and then
follow those many channel entries
If no. of channel entries does not match to count then it is
considered as error
To detect this, add a counter while adding channel entries and
give warning if channel count does not match with this counter
bug 1470692
Change-Id: I4bbfd9b696fbfafa25dffb27979373f057a7f35a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/449228
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Currently we clear the runlist and re-create it in
scheduled work during fifo recovery process
But we can post-pone this runlist re-generation for
later time i.e. when channel is closed
Hence, remove runlist locks and re-generation from
handle_mmu_fault() methods. Instead of that, disable
gr fifo access at start of recovery and re-enable
it at end of recovery process.
Also, delete scheduled work to re-create runlist.
Re-enable EPLG and fifo access in
finish_mmu_fault_handling() itself.
bug 1470692
Change-Id: I705a6a5236734c7207a01d9a9fa9eca22bdbe7eb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/449225
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Modify TSG's channel list as "ch_list" for all channels
instead of "ch_runnable_list" for only runnable list
We can traverse this list and check runnable status of
channel in active_channels to get runnable channels
Remove below APIs as they are no longer required :
gk20a_bind_runnable_channel_to_tsg()
gk20a_unbind_channel_from_tsg()
While closing the channel, call gk20a_tsg_unbind_channel()
to unbind the channel from TSG
bug 1470692
Change-Id: I0178fa74b3e8bb4e5c0b3e3b2b2f031491761ba7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/449227
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Currently if pmu_mutex_acquire() fails, we disable ELPG
and move ahead. But it is not clear why it is required
to disable ELPG in case where we fail to acquire mutex.
Hence skip disabling ELPG if mutex_acquire() fails
Bug 1533644
Change-Id: I7e8e99a701d0ba071eb31ac17582b04072ee55eb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/448131
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Channel and gpfifo allocations are entirely separated from each
other, however, the code here assumes that active channel means
that the channel also has a gpfifo.
This reverts commit a24602f094380539788696d1b1567a4f4d914b17 which
added gpfifo dump. Changing debug dumping to be safe requires
refactoring the channel release code to use proper locking.
Bug 1530226
Change-Id: I2fb02542a17dd56a0a9ce732b327e34b85ade8b9
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/434038
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Wait for engine idle via FIFO's engine status instead of submitting
WFI to channel. Submitting WFI and waiting is not robust, and wait
might invoke debug dump which cannot be done while powering down.
Bug 1499214
Change-Id: I4d52e8558e1a862ad4292036594d81ebfbd5f36b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/432151
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
- when a TSG channel is made runnable, add it to TSG's
runnable list
- when a TSG channel is removed from runlist, remove it
from TSG's runnable list
When we rewrite the entire runlist :
- first add all the channels which are not part of any TSG
- then find all active TSGs, add an entry in runlist for the TSG
(with TSG id and length of TSG)
- then write entries for each channel in that TSG
Bug 1470692
Change-Id: Ic55a4d5959abc72cd20b8224eb4c31d3ff411861
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/416612
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
When outputting debug dump, print the contents of current push buffer
segment.
Also changes the debug dump to use pr_cont when applicable, and dumps
state before recovering in case channel was not loaded to an engine.
Bug 1498688
Change-Id: I5ca12f64bae8f12333d82350278c700645d5007e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/422198
Implement a full L2 flush (clean and invalidate) for gm20b in
the fifo recovery path.
Bug 1512176
Change-Id: Ibf89ede9cca65a6868ebff89825869053302a007
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/416435
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
When aborting jobs on channel error situations, we manually set
the channel syncpoint's min == max in gk20a_disable_channel_no_update.
Nvhost will notice this manual syncpoint increment, and will call back
to gk20a_channel_update, which will clean up the job.
With semaphore synchronization, we don't have anybody calling back to
gk20a_channel_update, so we need to call it ourselves. Release job
semaphores (the equivalent of set_min_eq_max) on
gk20a_disable_channel_no_update, and if any semaphores were released,
call gk20a_channel_update afterwards.
Because we are actually calling gk20a_channel_update in some situations,
gk20a_disable_channel_no_update is no longer an appropriate name for the
function. Rename it to gk20a_channel_abort.
Bug 1450122
Change-Id: I1267b099a5778041cbc8e91b7184844812145b93
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/422161
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
In error case we first disabled the channel, and reset sync point to
max. After this we set channel error state. This causes a race if
channel is closed between setting sync point and setting channel
state.
Rearrange the code so that error state is set first, and only then
channel is disabled.
Bug 1519646
Change-Id: I20550f6a2708f892b6ba4ee714e90bdecdd128ad
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/418948
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
On PBDMA error even though the engine might not be wedged, we need to
kick the channel out of engine. Add that logic. Also when channel is
not in engine, we need to remove it from runlist.
Bug 1498688
Change-Id: I5939feb41d0a90635ba313b265c7e3b5d3f48622
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/417682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Even though we mask LBREQ interrupt, hardware will still indicate it
in PBDMA interrupt register. Stop treating LBREQ as fatal.
Bug 1498688
Change-Id: Iec4c199437c50951ed9289cb85faf0008646d5c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408763
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
Lbreq interrupt can assert when there is memory back pressure. Do not
enable it as either stalling or nonstalling interrupt.
Bug 1498688
Change-Id: I02f94a64ab9df82402d80a632450d87457644d50
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408040
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Add abstraction for triggering fake MMU fault, and a gk20a
implementation. Also adds recovery to FE hardware warning
exception to make testing easier.
Bug 1495967
Change-Id: I6703cff37900a4c4592023423f9c0b31a8928db2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
