Add a gops_gin struct for handling chip-specific GIN functionality. For
now, it only has the get_intr_ctrl_msg HAL. Each per-unit INTR_CTRL
register holds an opaque 32-bit value that determines how an interrupt
is routed. The layout of this value is determined by GIN. This HAL
allows units to ask GIN how it should program their INTR_CTRL registers.
Jira NVGPU-9217
Change-Id: I18f86e09701634bdb39db6b6e4728cd3595caa02
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839755
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- During nvgpu module unload, the poweroff sequence
will not wait for the ACK from the PMU for the RPCs sent.
- Due to this, rpc_payload struct info will be present
in pmu seq struct.
- This can lead to memory corruption during unload path.
- To avoid this, return a different value for driver shutting
down scenario from fw ack function and based on this return value
free the RPC payload and release the respective pmu sequence struct.
Bug 3789998
Change-Id: I25104828d836ae37e127b40c88209da81754ffb8
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Upstream Linux kernel commit ff62b8e6588f ("driver core: make struct
class.devnode() take a const *") updated the 'devnode' function pointer
under the class structure to take a const device struct. This breaks
building the NVGPU driver with Linux v6.2. Make the necessary changes to
the NVGPU driver to fix the build breakage.
Bug 3936429
Bug 3844023
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Change-Id: Ia39d7fded8df0e4eb30ebd58b2261e48e1963549
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2841032
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
When a user-domain gets removed, tsg belongs to this also gets removed
and runlist update happens accordingly. If same tsg was submitted to gpu
then updated runlist also needs to re-submit. This works fine with the
existing legacy cases but if GPU is running the shadow domain submitted
by manual mode scheduler and domain belongs to this gets removed then
updated runlist is not being submitted to GPU. This runlist buffer
inconsistency causes mmu fault later.
This change adds a "remove" field in the runlist domain which gets set
to true when runlist update happens for the channel removal. Later
worker thread submit the updated runlist if this flag set to true.
Bug 3884011
Change-Id: I3ce08a5a281e20661915746e70ac0dcd711f3f38
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2838808
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
There are three issues with shadow domain submission:
1. runlist mem is not being swapped with mem_hw for shadow domain when
there is non-shadow domain being bound to tsg which does not allow runlist
to have all the tsgs. To fix this nvgpu_runlist_swap_mem() is being called
for shadow domain as well.
2. tsg num_active_channels is being set as part of non-shadow domain which
does happen after shadow domain. Due to this, runlist tsg length is not
being set as part of runlist reconstruct and leaving tsg length 0 for last
tsg. To fix this, tsg num_active_channels always get set for shadow domain
as it gets configured first.
3. NV_BUILD_CONFIGURATION_VARIANT_IS_EMBEDDED is not solving the purpose
to differentiate l4t and embedded_linux builds so using
NV_BUILD_SYSTEM_TYPE in place of this to find out the build type.
L4t is using round robin scheduling and this issue coming with manual mode
scheduling so adding the fix only for manual mode scheduling support.
Bug 3884011
Change-Id: Ic55da8f75294eb32c8df6e35fb1fa47df78db8f8
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2833880
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
hw register checker detects and error on local setup by nvdvms team.
register readout in GVS and nvdvms team setup is different.
On Finial System, Checker is expected to run after init
But on GVS, Checker runs as a test case along with test other GPU tests.
This lead to mismatch between local and gvs testing.
register missmatch detected by an hw register checker is not really
an error, its related to information.
There are two cases for updating mask value
1. These interrupts are mainly for sw information not any errors
2. These are temporary values ready from board
We will update these values again once we get finial list from HW team
so, we can avoid checking bits 4:7, which represents
* NV_RUNLIST_INTR_0_RUNLIST_IDLE 4U:4U /* RWIVF */
* NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE 5U:5U /* RWXVF */
* NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE 6U:6U /* RWXVF */
* NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE 7U:7U /* RWXVF */
Bug 3912656
Change-Id: I75d1d4737897ef44e78329ed708e86637e8bcf48
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2831273
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This patch introduces the flag NVGPU_DISABLE_STATIC_POWERGATE. Further,
static pg related initialization APIs have been updated to check whether
this newly added flag is enabled. If this flag is enabled, then static
pg init gets skipped.
JIRA NVGPU-9350
Change-Id: I450b6dd2c541d31fc40fb5540e557b5db730fee2
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2834021
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
gv11b onwards add hals
get_hwpm_gpcrouter_perfmon_regs_base
get_hwpm_fbprouter_perfmon_regs_base
And remove the ga10b version of same as that is redundant.
This is preparatory patch to update the gr_gv11b_pri_pmmgpcrouter_addr
and gr_gv11b_pri_pmmfbprouter_addr with the hals
JIRA NVGPU-9073
Change-Id: I8b04f9b61784ca2c09b248655435ea7a7ab92926
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2828584
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This change is to adapt to shift of ACR t234 safety code from
iGPU to dGPU.
Required changes consists of:
Adding support for new LSB, WPR and ACR descriptor structures
which are more aligned with what dGPU currently uses.
Change old riscv LSB header to version 1, as version 2 will
be used for new header to align with dGPU header nomenclature.
Jira NVGPU-9298
Change-Id: Id75f7d0a03dc65c1983822ead428b330a83481a1
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2811116
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Currently the gsp scheudler is enabled for all linux configurations and
this change will enable the gsp scheduler on embedded linux profile and
will disable on l4t.
One of the gsp ga10b hal funcion is used by nvgpu-next so the defination
is moved out of gsp scheduler flag
NVGPU-9297
Change-Id: If457db46e26d8f5be01f643c75a22aafb86bd7f3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2826152
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
The patch is adding a OS specific call to get the supported
syncpoints from the DT entry. The syncpoints is used to
initialize the number of supported channels while GPU
initialization.
The error path is taken care with the default value 256.
As device tree entries not available in upstream, the path
handled with the default value 256.
Change-Id: I9ac949d68a9f93f0e56fdbf8c8cd33b7dc903298
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2826280
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
