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342 Commits

Author SHA1 Message Date
David Nieto
e78cd6c42a gpu: nvgpu: add missing hal defines 
Due to lack of GVS coverage some defines were left out in GV100, this change
adds them back

JIRA: NVGPUGV100-9

Change-Id: I2f5778529dcad535bb56c33c38c097415dbf11e5
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577998
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
 2017-10-16 23:34:04 -07:00
Terje Bergstrom
0c40a3e034 gpu: nvgpu: Initialize usermode regs for Volta dGPU 
Initialize usermode registers also for Volta GPU behind PCIe.

Change-Id: Id621a74838839e4d98dfd0828c1ea5a0d54baa2d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1579121
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Tested-by: David Martinez Nieto <dmartineznie@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
 2017-10-16 13:35:12 -07:00
Peter Daifuku
4b8dc71de5 gpu: nvgpu: vgpu: flatten out t19x vgpu hal 
Instead of calling the native HAL init function then adding
multiple layers of modification for VGPU, flatten out the sequence
so that all entry points are set statically and visible in a
single file.

JIRA ESRM-30

Change-Id: I8d277aaccb0e63b2d504e7aba32eb31ef82f4ec0
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574619
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-10-13 15:20:19 -07:00
seshendra Gadagottu
7612e41215 gpu: nvgpu: gvxx: add hw defines for pbdma info 
Generated following hw definitions to dump relevant data:
    pbdma_gp_shadow_0_r
    pbdma_gp_shadow_1_r

Bug 2003671

Change-Id: If2d0557b3c2896747793ff2afad875206e25c6d8
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1572183
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-10-13 15:20:12 -07:00
Terje Bergstrom
b0092ea95c gpu: nvgpu: gv11b: Abstract IO aperture accessors 
Implement T19x specific usermode aperture initialization functions.
Move usermode_regs field to nvgpu_os_linux_t19x, because it is
Linux specific.

JIRA NVGPU-259

Change-Id: I9d6ce243a692ab48209d468288ed85f89fb26770
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569699
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-10-13 15:20:01 -07:00
seshendra Gadagottu
506f891f76 gpu: nvgpu: gv11b: add syncpt shim ro map 
For sync-point read map, create read only map per vm
and share with all channels that are using same vm.

Now restrict rw map to single syncpoint shim memory range.

JIRA GPUT19X-2

Change-Id: Ibd0b82d1cdb8861e1dbb073b27da1f9c9ab1d2ab
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514339
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-10-13 15:19:17 -07:00
Timo Alho
a693acc5b4 Revert "gpu: nvgpu: gv11b: disable cycle stat" 
This reverts commit 6647e5c956.

Bug 200352825

Change-Id: Ia44d61eafce78f99be2271e0afaf69cd5c102080
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577920
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srikar Srimath Tirumala <srikars@nvidia.com>
 2017-10-12 13:46:09 -07:00
Terje Bergstrom
82f235b529 gpu: nvgpu: gv100: Qualify unsigned HW constants 
Re-generate hardware headers so that all unsigned constants are
qualified with postfix U. This removes the need for compiler to do
implicit signed->unsigned conversions.

Change-Id: If3c1e25dcb07ce6857a4798f2c5308e2948fe5e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1571163
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2017-10-11 21:08:15 -07:00
Alex Waterman
ade9f5e03f gpu: nvgpu: Remove phys_addr_t from common code 
Remove phys_addr_t change for corresponding change in the nvgpu
main repo.

JIRA NVGPU-30
JIRA NVGPU-226

Change-Id: I05a19bc51e949279edef6e9ad7161226cbca51a7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576466
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-10-11 14:40:23 -07:00
Terje Bergstrom
514c80d8d2 gpu: nvgpu: gv11b: Qualify unsigned HW constants 
Re-generate hardware headers so that all unsigned constants are
qualified with postfix U. This removes the need for compiler to do
implicit signed->unsigned conversions.

Change-Id: Ic93ef7f7a6beae57be7759c7eb3df9148afed824
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1571162
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
 2017-10-10 16:26:52 -07:00
David Nieto
f518304e0d gpu: nvgpu: fix GV100 hal definitions 
These changes allow GV100 to init the basic HALs to pass
nvgpu_submit_twod

(1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency
issues
(2) Properly enable FB
(3) Fan control requires the execution of the pre-os FW, without it the SKU201
is extremely noisy

 JIRA: NVGPUGV100-9

Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1539926
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-10-10 12:05:41 -07:00
Seema Khowala
bb1c38e2f5 gpu: nvgpu: gv11b: perfbuffer enable and disable dbg ops set to NULL 
Will be enabled after feature is verified on volta

Bug 200352825

Change-Id: Idbe318ea82051e53f15caecf2afb15d72b99acea
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574482
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-10-10 09:24:46 -07:00
Seema Khowala
6647e5c956 gpu: nvgpu: gv11b: disable cycle stat 
Feature will be enabled after it is verified.
To disable cycle stat, do not set
NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS and
NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT

Bug 200352825

Change-Id: I3f0d58a8095f3a0996964056029c12cff45f0a5b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1573760
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-10-10 09:22:08 -07:00
Seema Khowala
6fe9bdeb9a gpu: nvgpu: gv11b: track init veid bundle 
Add debug prints to track veid bundle init
and also return err for subctx init failure.

Bug 1983643

Change-Id: I9e6a32e76b1c7deba3a47157ba253976d88b2324
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1568070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-10-10 08:10:37 -07:00
Deepak Nibade
19d602da31 gpu: nvgpu: verify channel status while closing per-platform 
We right now call gk20a_fifo_tsg_unbind_channel_verify_status() to verify
channel status while unbinding a channel from TSG while closing

Add support to do this verification per-platform and keep this disabled
for vgpu platforms

Bug 200327095

Change-Id: I6e2a6a09c784d24ac49477d5450b7d4b671878e3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1572369
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-10-04 03:43:18 -07:00
Mahantesh Kumbar
a616611727 gpu: nvgpu: falcon: Qualify unsigned HW constants 
- Falcon HW header re-generate for gv11b.
- Re-generate hardware headers so that all unsigned
  constants are qualified with postfix U. This removes
  the need for compiler to do implicit signed->unsigned
  conversions

Change-Id: I313945edac1112a32c965d9565b30dc95a002752
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1571352
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2017-10-04 03:40:30 -07:00
Mahantesh Kumbar
3663e9cccc gpu: nvgpu: gv100 hw header for Falcon controller 
- Constants are qualified with postfix U.
This removes the need for compiler to do
implicit signed->unsigned conversions

Change-Id: I039e269b18ea8aea48b30d3af84b347ae5509413
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570998
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2017-10-04 03:40:20 -07:00
Alex Waterman
dc5edb1417 gpu: nvgpu: rename ops.mm.get_physical_addr_bits 
T19x/gv100 version of same patch in kernel/nvgpu.

Change-Id: I7174864cf1e072af61609c0843da16fcafe54c02
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566750
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-10-04 02:32:32 -07:00
Deepak Goyal
192afccf7c gpu: nvgpu: gv11b: skip clk gating prog for pre-si 
For pre-silicon platforms, clock gating
should be skipped as it is not supported.
Added new flags "can_"x"lcg" to check platform
capability before programming SLCG,BLCG and ELCG.

Bug 200314250

Change-Id: Iec7564b00b988cdd50a02f3130662727839c5047
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566251
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-10-04 02:27:12 -07:00
Seema Khowala
f63f96866d gpu: nvgpu: gv11b: init therm regs for pwr/clk 
init *eng_delay*, *eng_idle_filt*, *fecs_idle_filter*
and *hubmmu_idle_filter* in therm regs.

Change-Id: I4ab5374084e993cd96ef28ace87b6013b996178d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570556
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2017-10-03 13:35:48 -07:00
seshendra Gadagottu
058485d285 gpu: nvgpu: gv100: disable ctxsw trace 
ctxsw_trace need modifications with subcontext.
Disable it for time-being.

Change-Id: I0f0e3d0653e159dca09c40c8d0b4c46643cd0496
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569629
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Tested-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-10-03 13:33:03 -07:00
seshendra Gadagottu
0d63e22a99 gpu: nvgpu: gv11b: check for memory aperture type 
Check for memory aperture type before setting relevant
sysmem non-coherent or vidmem flags in ram entry.

Modified following functions to correct memory aperture type:
gv11b_get_ch_runlist_entry
gv11b_subctx_commit_pdb

Added following hw constants for chan_inst_target:
ram_rl_entry_chan_inst_target_sys_mem_coh_v
ram_rl_entry_chan_inst_target_vid_mem_v

Change-Id: I85698044b9fe4c8baed71121845e4fb69dc33922
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569521
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-10-03 13:33:00 -07:00
seshendra Gadagottu
1f6755b287 gpu: nvgpu: gv11b: set correct max subctx count 
Reading gr_pri_fe_chip_def_info_r() during
gv11b_init_fifo_setup_hw on RTL platforms is giving
"0xbadf1201" error because fecs part of priv ring
is still in reset. This needs to be fixed after
identifying relevant engine that needs to be
brought out of reset. Until that time, use constant
value from hw definition(whose value is 64):
gr_pri_fe_chip_def_info_max_veid_count_init_v().

Bug 1983643

Change-Id: I66f2b6491c9d444c6f6919e76c72ec33a904bc90
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1568139
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-09-26 17:29:26 -07:00
seshendra Gadagottu
9825a8ec69 gpu: nvgpu: fix handling of EGPC_ETPC_SM addresses 
Implemented litter values for following defines:
GPU_LIT_SMPC_PRI_BASE
GPU_LIT_SMPC_PRI_SHARED_BASE
GPU_LIT_SMPC_PRI_UNIQUE_BASE9
GPU_LIT_SMPC_PRI_STRIDE

Added broadcast flags for smpc

Handled all combinations of broadcast/unicast EGPC, ETPC, SM

Bug 200337994

Change-Id: I7aa3c4d9ac4e819010061d44fb5a40056762f518
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1539075
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-09-26 17:29:23 -07:00
Richard Zhao
971987f363 gpu: nvgpu: vgpu: unset gops->fifo.tsg_verify_status_faulted 
The native code of fault checking accesses channel registers
which is impossible for vgpu.
vgpu needs to implement its own later.

Bug 200349281

Change-Id: Iea78ad5457bcc30d0545bbe2e1cd1dba76ed2680
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1564715
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-09-26 16:00:05 -07:00
Terje Bergstrom
d61643c020 gpu: nvgpu: gv11b: Change license for common files to MIT 
Change license of OS independent source code files to MIT.

JIRA NVGPU-218

Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1567804
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2017-09-25 17:03:31 -07:00
Terje Bergstrom
c359afbfe2 gpu: nvgpu: Change HW header licenses to MIT 
JIRA NVGPU-218

Change-Id: I7e506649a5e32c54bf6880b575dedb63097ebb1b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565708
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-09-25 09:09:22 -07:00
Mahantesh Kumbar
39eb00deda gpu: nvgpu: gv11b faclon hw header update 
- Update CPUCTL register to add soft/hard reset support
- Added debug registers

JIRA NVGPU-56

Change-Id: Id867dd3a6085131917c2ada88f9899e415348038
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1564156
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2017-09-25 00:19:03 -07:00
David Nieto
4d5216922b gpu: nvgpu: fix coverity issues in GV100 HAL 
Fix value overwrite in switch statement on GV100 proj assignments

bug 200291879

Change-Id: Id25f811f820a05b3d50cc9070369fe52f65a6bf3
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565538
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-09-22 11:29:13 -07:00
Mahantesh Kumbar
a24382d097 gpu: nvgpu: Add support for WPR info read from FB 
update .read_wpr_info HAL of gv11b & gv100
 to point to gm20b_fb_read_wpr_info()

JIRA NVGPU-128

Change-Id: I5ece4c72dbe0f9e7827888e2a15d8b7dda6fcb42
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1564684
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2017-09-22 06:14:03 -07:00
Sreejith V
ca2560af80 gpu: nvgpu: gv11b: remove misleading intendation warning 
Bug 200348860
Bug 200291879

Change-Id: Ia1e651d8365eae6e7aef69d79923d644c7067211
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563869
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-09-20 15:58:08 -07:00
Alexander Lewkowicz
1586a9f004 gpu: nvgpu: gv11b: Fix sm lock down 
Volta traphandler RM changes

Sm lock-down is not being executed correctly. This results in a
GPU being in an undefined state. A similar bug fix was already
provided on the resman implementation. This fix is inspired by the
CL change 21183102.
That change refers to bug http://nvbugs/1800484 and bug
http://nvbugs/200162542

This patch solves the issues mention in bug http://nvbugs/1992522

Change-Id: I601fef7c94e5ba419d7bf854877fa7a9f9b82cfa
Signed-off-by: Alexander Lewkowicz <alewkowicz@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563815
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-09-20 15:58:08 -07:00
Terje Bergstrom
0a0da216db gpu: nvgpu: Use VBIOS HAL from gp106 instead of gm206 
Use VBIOS HAL from gp106 instead of gm206.

JIRA NVGPU-218

Change-Id: I835a1ce39818221f976ed5eca2bf3032317760b0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563741
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-09-20 15:52:56 -07:00
seshendra Gadagottu
b454d30d89 gpu: nvgpu: gv11b: enable per veid header for subctx 
Enable per veid header mode for subcontext header.

Allocated only context header size for subcontext
header.

Bug 1958308

Change-Id: I6b45987eed968252326a366650fefd807975b70f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562681
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2017-09-19 17:45:30 -07:00
seshendra Gadagottu
0420dd383e gpu: nvgpu: gv11b: Initialize ctxsw hdr counters 
Initlize following context  switch header counters for
gv11b:
ctxsw_prog_main_image_num_save_ops
ctxsw_prog_main_image_num_restore_ops
ctxsw_prog_main_image_num_wfi_save_ops
ctxsw_prog_main_image_num_cta_save_ops
ctxsw_prog_main_image_num_gfxp_save_ops
ctxsw_prog_main_image_num_cilp_save_ops

Reused gp10b gr hal function gr_gp10b_init_ctxsw_hdr_data()
for this.

Bug 1958308

Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I10d83e35ccd8cba517ebaba1f0e5bec5a0f68ba5
Reviewed-on: https://git-master.nvidia.com/r/1562655
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2017-09-19 17:45:28 -07:00
seshendra Gadagottu
cedb24c7a0 gpu: nvgpu: gv11b: correct wl reg offset 
Corrected whitelist register address offset for
gr_pri_gpcs_tpcs_sm_disp_ctrl. This offset value is
changed for gv11b from gp10b. With wrong offset value,
gl tests are generating "unhandled fecs error interrupt
0x00000002 for channel xxx".

Bug 1958308

Change-Id: Iabfbb20ea1ee4ca8567d0cda940fa1e8cbff1bac
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562615
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2017-09-19 17:45:27 -07:00
Seema Khowala
e4e6a4a734 gpu: nvgpu: gv11b: remove double declaration 
gv11b_fb_fault_buf_configure_hw is declared twice. Fix
the same by removing one of the declarations.

Change-Id: I12a857b4225164067f0329530249ffc0dcdc1412
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
 2017-09-18 18:19:08 -07:00
Seema Khowala
1c850d0bee gpu: nvgpu: gv11b: fecs_trace ops are set to NULL 
CTXSW_TRACE will be enabled only after it is
verified. Set all function pointers for fecs_trace
to NULL

JIRA GPUT19X-42

Change-Id: I7a807f997f683c19541e55fa7e3d5d3ff6b645d2
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1558464
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-09-15 15:16:00 -07:00
Seema Khowala
622072d1c0 gpu: nvgpu: gv11b: poll tsgid for preempt done 
Use tsgid for polling preemption completion since
id and next_id in pbdma and eng status point to
tsgid

Bug 200277163
Bug 1958308

Change-Id: I5636ce1f8b21ddac4c93d92ce0527fe0307f2cfc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1557253
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-09-15 15:13:24 -07:00
Seema Khowala
31a50f07e4 gpu: nvgpu: gv11b: Set pbdma, fb and ctxsw timeout for pre-si 
fb and ctxsw timeout detection should be disabled for simulation
architectures. Also set timeouts to max for pbdma, fb and
ctxsw timeouts.

Bug 200289427

Change-Id: I8723d5ee9ea2535f401b1972c8c14ffab8f9504a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549522
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-09-15 15:10:48 -07:00
Deepak Nibade
f720b309f1 gpu: nvgpu: add tsg_verify_status_faulted operation 
Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as
g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100

This API will check if channel has ENG_FAULTED status set, if yes it will clear
CE method buffer in case saved out channel is same as faulted channel
We need to write 0 to method count to invalidate CE method buffer

Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100

Bug 200327095

Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560643
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-09-15 12:48:22 -07:00
Deepak Nibade
52f50addc6 gpu: nvgpu: add TSG enable/disable operations 
Add TSG enable/disable operations for gv11b/gv100

To disable a TSG we continue to use gk20a_disable_tsg()

To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is
different for Volta than previous versions
For Volta it is sufficient to loop over all the channels in TSG and enable them
sequentially

Bug 1739362

Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560642
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-09-15 12:48:21 -07:00
Mahantesh Kumbar
56d03664d0 gpu: nvgpu: GV100 fecs/gpccs sign file path 
- Added paths of GV100 fecs/gpccs sign file.

JIRA NVGPUGV100-7

Change-Id: I92d1fa51c1e66b3eb4009a0a51f6f3252cba41d9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549424
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-09-12 15:57:24 -07:00
Terje Bergstrom
f98e3c8348 gpu: nvgpu: gv100: Don't assign XVE sw_init 
XVE sw_init HAL is removed due to moving XVE debugfs code to
Linux module. Remove the assignment of the HAL.

Change-Id: I90beada58f87c78dc752011ea3ec2a5473f0acc1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1553913
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
 2017-09-12 13:00:19 -07:00
Deepak Goyal
91a8522999 gpu: nvgpu: gv11b: add ops for getting timestamp. 
assign GPU bus ops for getting timestamps using PTIMER.

BUG 1957272

Change-Id: I1ded165858849a6a93e6ae0617ec1423d48f75ed
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1555528
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2017-09-11 10:34:59 -07:00
Konsta Holtta
58018f0c1b gpu: nvgpu: gv11b: hold ch ref when getting ch from fd 
Add gk20a_channel_put() pair for gk20a_get_channel_from_file() that now
returns the channel with a reference.

Also fix resource leaks in gv11b_tsg_ioctl_bind_channel_ex's error
paths.

Change-Id: Ib348219defa67163657ca534826f504ebc59497e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1553276
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-09-11 10:34:58 -07:00
seshendra Gadagottu
a42d6029a5 gpu: nvgpu: gv11b: correct logic to get num of pce 
Correct the logic to get number of physical
copy engines supported in gv11b.

Change-Id: I02e0628364d056121d08dfcd0ddfb0c013207d4b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1544207
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2017-09-01 03:19:41 -07:00
Deepak Goyal
c094ea1617 gpu: nvgpu: gv11b: Secure boot support. 
This patch adds Secure boot support for T194.

JIRA GPUT19X-5

Change-Id: If78e5e0ecfa58bcac132716c7f2c155f21899027
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514558
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2017-08-31 01:55:06 -07:00
Richard Zhao
1ac8f6477d gpu: nvgpu: vgpu: add TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 
Get max subctx count from RM server.

Jira VFND-3797

Change-Id: I95de2271a77bedfa8703231fa45da05c7d2da3e6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1543018
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2017-08-28 17:04:31 -07:00
Sunny He
866165749a gpu: nvgpu: Reorg gr HAL initialization 
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
gr sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1542988
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-08-24 09:34:43 -07:00