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8 Commits

Author SHA1 Message Date
Vedashree Vidwans
068e00749b gpu: nvgpu: update config_userd_writeback_enable 
Field value of pbdma_config_userd_writeback_enable is changing from
0x1 to 0x0 for nvgpu-next. So,
- Update config_userd_writeback_enable() hal to accept u32 value.
- Update config_userd_writeback_enable() hal to return modified
  value after setting pbdma_config_userd_writeback_enable field.

Jira NVGPU-5162

Change-Id: I94efa20c34bb867f185778c973bd52b86902b32c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2330160
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs 
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2019-05-06 02:56:53 -07:00
Thomas Fleury
157b43ed16 gpu: nvgpu: clean ramfc dependencies 
Remove ramfc dependencies on fifo hw header.

Added the following HALs:
- fifo.get_runlist_timeslice
- fifo.get_pb_timeslice

Jira NVGPU-3199

Change-Id: I1bdd4ee5e4008676df514b9d8563e862d1d68e33
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104539
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 2019-04-25 16:26:57 -07:00
Seema Khowala
192b5c5569 gpu: nvgpu: move fifo_gv11b.[ch] to hal/fifo 
Move fifo_gv11b.[ch] to hal/fifo and clean up
include directives

JIRA NVGPU-1314

Change-Id: I42346ea93360e4b5023eda7538406275eb583d13
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102929
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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 2019-04-24 20:23:18 -07:00
Debarshi Dutta
8e96d56cee gpu: nvgpu: add ramfc specific pbdma hal functions 
Only one h/w header is allowed per hal file. ramfc_*.c uses both
hw_ramfc_*.h and hw_pbdma_*.h. The pbdma dependencies are removed from
the HAL unit of ramfc by constructing new HAL functions for pbdma unit.
The HAL ops functions added are listed below.

get_gp_base
get_gp_base_hi
get_fc_formats
get_fc_pb_header
get_fc_subdevice
get_fc_target
get_ctrl_hce_priv_mode_yes
get_userd_aperture_mask
get_userd_addr
get_userd_hi_addr
get_fc_runlist_timeslice
get_config_auth_level_privileged
set_channel_info_veid
config_userd_writeback_enable
allowed_syncpoints_0_index_f
allowed_syncpoints_0_valid_f
allowed_syncpoints_0_index_v

These HAL ops uses the following new implementations.

gm20b_pbdma_get_gp_base
gm20b_pbdma_get_gp_base_hi
gm20b_pbdma_get_fc_formats
gm20b_pbdma_get_fc_pb_header
gm20b_pbdma_get_fc_subdevice
gm20b_pbdma_get_fc_target
gm20b_pbdma_get_ctrl_hce_priv_mode_yes
gm20b_pbdma_get_userd_aperture_mask
gm20b_pbdma_get_userd_addr
gm20b_pbdma_get_userd_hi_addr

gp10b_pbdma_get_fc_runlist_timeslice
gp10b_pbdma_get_config_auth_level_privileged
gp10b_pbdma_allowed_syncpoints_0_index_f
gp10b_pbdma_allowed_syncpoints_0_valid_f
gp10b_pbdma_allowed_syncpoints_0_index_v

gv11b_pbdma_get_fc_pb_header
gv11b_pbdma_get_fc_target
gv11b_pbdma_set_channel_info_veid
gv11b_pbdma_config_userd_writeback_enable

Jira NVGPU-3195

Change-Id: I849f16650046eca38c67b0d6e0e43cd2ab1ac224
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102576
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-04-24 03:43:44 -07:00
Thomas Fleury
35e9663bd0 gpu: nvgpu: move eng_method_bufers from fifo to tsg 
Moved init/deinit eng method buffers from fifo to tsg
- tsg.init_eng_method_buffers
- tsg.deinit_eng_method_buffers

Moved gv11b_fifo_init_ramfc_eng_method_buffer to the
following tsg HAL:
- tsg.bind_channel_eng_method_buffers

This HAL is now called during bind_channel.

Added the following ramin HAL:
- ramin.set_ramfc_eng_method_buffer

Jira NVGPU-2979

Change-Id: I96f6ff15d2176d4e3714fa8fe65a9126b3fff82c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087185
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 2019-04-10 10:36:28 -07:00
Debarshi Dutta
993fbd085e gpu: nvgpu: update pbdma HAL Ops method names 
HAL ops specific to pbdma are now updated to remove the word "pbdma"
from the function names in order to follow the convention
g->ops.pbdma.{function_name}()

Jira NVGPU-2950

Change-Id: I43ddb5c842b31c97da8fe35f4762de0478916702
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075438
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 2019-04-01 10:14:25 -07:00
Thomas Fleury
1701a267bc gpu: nvgpu: move setup ramfc code to common 
Create ramfc under common/fifo

Created the following HAL:
- ramfc.setup
- ramfc.commit_userd

Moved setup code to ramfc HAL:
- vgpu_channel_setup_ramfc
- gk20a_fifo_setup_ramfc
- channel_gp10b_setup_ramfc
- channel_gv11b_setup_ramfc
- channel_tu104_setup_ramfc

Renamed as:
- <chip>_ramfc_setup

Moved commit userd code to ramfc HAL:
- gk20a_fifo_commit_userd
- channel_gp10b_commit_userd

Renamed as:
- <chip>_ramfc_commit_userd

Jira NVGPU-1750

Change-Id: Ieb1bd2866fd77601edd218f879ababf4f90db54a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069947
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-03-27 20:35:04 -07:00