SEC2 isr handling requires message processing in common msg unit. That
unit requires interfaces from hal to know if the msg interrupt was
received, set the msg interrupt and handle other interrupts.
JIRA NVGPU-2025
Change-Id: I3b5ad8968ea9298cc769113417931c4678009cf1
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085753
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
SEC2 message handling unit can't be part of command handling unit as it
creates circular dependencies with the SEC2 tasks (ACR bootstrap)
SEC2 allocator unit shall encompass DMEM allocator and other allocators
used by SEC2.
JIRA NVGPU-2075
Change-Id: Ic2b8204d8225f2056785f035cbecdb776a9ecfe9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085749
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
