Remove branch F_CHANNEL_SETUP_BIND_HAS_GPFIFO_MEM from the unit test
for nvgpu_channel_setup_bind as gpfifo_mem belongs to KMD and are not
part of safe builds.
Remove assignment of stub_userd_setup_sw as USERD is compiled out for
safe build.
Jira NVGPU-3172
Change-Id: I4ba72043cb97d8804887c2bed30af9d01dca563e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2142941
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Statically initialized nvgpu_posix_io_reg_space structures are
used in test_fifo_setup_gv11b_reg_space to initialize register spaces.
If fifo, TSG and channel unit tests run concurrently, the same
register space structure can be registered multiple times for
different GPU contexts. This results in list corruption or
use of freed memory.
Use allocated register spaces instead.
Jira NVGPU-3943
Change-Id: I74c080f336e32149d2a378e2b15d37a2bd60ff71
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204062
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Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Rename gr register space allocation and deallocation functions
to test_gr_init_setup and test_gr_remove_setup
Add tests to support following functions
nvgpu_gr_init
nvgpu_gr_init_support
nvgpu_gr_suspend
nvgpu_gr_remove_support
Jira NVGPU-3970
Change-Id: I11418ddcb9946ef75de162fd5689fdbbbfb62e79
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194612
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When the non-FUSA HALs were removed, the entire fuse unit test was
removed. However, some of the fuse HALs are used in the FUSA build, so
re-enable the FUSA tests, as appropriate.
JIRA NVGPU-3943
Change-Id: I6656940492102ace335672466592b22ed9ce95fd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194569
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The tests test_fuse_*_check_sec_invalid_gcplex were dependent on a
previous test setting up the HAL override for reading the gcplex fuse.
This updates the test_fuse_*_check_sec_invalid_gcplex tests to set this
override themselves to avoid issues if the tests are ever reordered.
JIRA NVGPU-3943
Change-Id: I3da14badd4cf0e310260cbbed98700660ef99e28
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195231
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Move gr_init_prepare to separate gr unit test
Use of global register spaces between two different
gr unit tests corrupt the memory in multi thread support.
Add support for local register spaces with pre initialized
register values for each gr unit test.
Jira NVGPU-3582
Change-Id: I4e47c1ca4f312335cd33a73a377f9fa9f12ccd5f
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189502
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Add support gr_prepare for sw and hw.
Add needed registers using nvgpu_posix_io_add_reg_space calls.
Add unit tests covering following functions
nvgpu_gr_prepare_sw
nvgpu_gr_enable_hw
install-unit.sh modified to copy the firmware binaries under
nvgpu-unit/firmware directory
Currently the gr_init_prepare test is called as part of the
gr_config test, later this will be moved as separate unit test.
Jira NVGPU-3582
Bug 2693908
Change-Id: If8f5ac4988deba0db477b2177981f7912bdb8eec
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191254
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The threaded tests for inc_and_test, dec_and_test, and sub_and_test were
not "passing" reliably for the "not_atomic" variants.
This updates these tests (atomic and non-atomic) to increase concurrency
of the operations by having each thread execute the operation 100 times
each rather than just once. For the sake of test time, it creates new
args for the threaded versions to keep iterations reasonable.
JIRA NVGPU-3954
Change-Id: I1fe2baa73ed1b9d4a8e13c97656411329b141db0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189347
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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This reverts commit 9bfdb2ba03f90f0cf828f08b99101a3a3e6c4532.
Bug 2693908
Change-Id: I3ef56773e46aad3626f16b84ea5e51c2fdcc3f1c
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189200
Add support gr_prepare for sw and hw.
Add needed registers using nvgpu_posix_io_add_reg_space calls.
Add unit tests covering following functions
nvgpu_gr_prepare_sw
nvgpu_gr_enable_hw
Copy the falcon ucode binaries under userspace/firmware
directory
install-unit.sh modified to copy the firmware binaries
under nvgpu-unnit/firmware directory
Jira NVGPU-3582
Change-Id: If2131d2c48e828251208da86688b0594e62de82e
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2184293
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add support for the fuse and gv11b_gr related
registers and with initialized values need for
gr_config tests.
Add unit tests covering following functions
nvgpu_gr_alloc
nvgpu_gr_config_init
nvgpu_gr_config_deinit
nvgpu_gr_free
Most of the gr_config.h get and set functions
will be used in config_check_set_get test
Jira NVGPU-3582
Change-Id: I69637b3047d844559ac5b44ffd366551af8ea12c
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2176369
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utf_falcons in libfalcon_utf.so are used by multiple unit tests and
since unit tests are run out of order it might lead to inconsistent
access to these structs.
Move these to falcon unit test. Updated the logic in the falcon utf
shared library to only export the interfaces to read/write to flcn
registers/memory.
JIRA NVGPU-2159
Change-Id: I3a1f80cce205747de4085802199ecc355bb95d6f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2174187
GVS: Gerrit_Virtual_Submit
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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Add nvgpu_utf_falcon_set_dmactl() function in falcon UTF
to set the falcon dmactl register with desired value
required for pmu reset test
Also, update the register size for falcon from 0x300 to 0x400
for including pmu reset register.
Rename userspace/units/facon/falcon folder to
userspace/units/facon/falcon_tests
JIRA NVGPU-2159
Change-Id: I0b22cff4699af6947e87019751aa85508dfdb185
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155124
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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