Rename gr register space allocation and deallocation functions
to test_gr_init_setup and test_gr_remove_setup
Add tests to support following functions
nvgpu_gr_init
nvgpu_gr_init_support
nvgpu_gr_suspend
nvgpu_gr_remove_support
Jira NVGPU-3970
Change-Id: I11418ddcb9946ef75de162fd5689fdbbbfb62e79
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194612
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Do some doxygen cleanup for the whitelisting macros:
- Previously doxygen documentation was being generated for the no-op
whitelisting macros. Enable the NV_IS_COVERITY define in the
doxygen build. This generates doxygen documentation for the actual
whitelisting macros.
- Create a doxygen group for the whitelisting macros. This adds
additional documentation for the whitelisting macros.
- Add doxygen line breaks
JIRA NVGPU-3820
Change-Id: Id452147a3a909da7981303d0908f2aff4a2ff86b
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194711
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When the non-FUSA HALs were removed, the entire fuse unit test was
removed. However, some of the fuse HALs are used in the FUSA build, so
re-enable the FUSA tests, as appropriate.
JIRA NVGPU-3943
Change-Id: I6656940492102ace335672466592b22ed9ce95fd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194569
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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The tests test_fuse_*_check_sec_invalid_gcplex were dependent on a
previous test setting up the HAL override for reading the gcplex fuse.
This updates the test_fuse_*_check_sec_invalid_gcplex tests to set this
override themselves to avoid issues if the tests are ever reordered.
JIRA NVGPU-3943
Change-Id: I3da14badd4cf0e310260cbbed98700660ef99e28
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195231
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Whitelisting changes for tmake are set at the top level in
tmake/umbrella/parts.tmk. The change in drivers/gpu/nvgpu/Makefile.tmk
is unnecessary. Therefore, the nvgpu change is being removed.
JIRA NVGPU-3820
Change-Id: I2053e69759df0d3dbf58b209a957d9227c1ebb40
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2193805
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reduce code complexity of gr falcon unit functions.
Rewrite the gm20b_gr_falcon_check_ctx_opcode_success and
gm20b_gr_falcon_check_ctx_opcode_failure function to use
gm20b_gr_falcon_check_ctx_opcode_status.
Reduce complexity of gm20b_gr_falcon_check_ctx_opcode_status function
by using following sub functions
gm20b_gr_falcon_check_valid_gr_opcode
gm20b_gr_falcon_gr_opcode_equal
gm20b_gr_falcon_gr_opcode_not_equal
gm20b_gr_falcon_gr_opcode_and
gm20b_gr_falcon_gr_opcode_less
gm20b_gr_falcon_gr_opcode_less_equal
Jira NVGPU-3975
Change-Id: I9dc6330e175e5200643dbfe177716cfd3df2d5c1
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2193651
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Some of the debugger and graphics specific functions were already
not being used in safety build. Compile out their definitions
and declarations as well.
Also, fail preemption set call if non-zero graphics preemption mode
is requested in safety build.
Jira NVGPU-3967
Change-Id: Iaf5e3bd58e6096da40301b79e9295a6c5893cd4a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191764
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Reduced MCC for nvgpu_netlist_init_ctx_vars_fw from 11 to 9 using
following helper function:
nvgpu_netlist_is_valid: MCC 3 TCC 3
Reduced TCC for nvgpu_netlist_init_ctx_vars_fw from 46 to 9 using
following helper functions:
nvgpu_netlist_handle_region_id : MCC 10 TCC 10
nvgpu_netlist_handle_ucode_region_id : MCC 2 TCC 5
nvgpu_netlist_handle_sw_bundles_region_id: MCC 2 TCC 7
nvgpu_netlist_handle_generic_region_id: MCC 2 TCC 5
nvgpu_netlist_handle_debugger_region_id: MCC 2 TCC 23
nvgpu_netlist_handle_debugger_region_id is not enabled for safety build
so higher TCC can be ignored.
JIRA NVGPU-3976
Change-Id: I38516b50642dd8c72aafc8795d9d336bb1bb1771
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2192959
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Move gr_init_prepare to separate gr unit test
Use of global register spaces between two different
gr unit tests corrupt the memory in multi thread support.
Add support for local register spaces with pre initialized
register values for each gr unit test.
Jira NVGPU-3582
Change-Id: I4e47c1ca4f312335cd33a73a377f9fa9f12ccd5f
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189502
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Reduce code complexity of gr_intr_handle_tpc_exception and
nvgpu_gr_intr_handle_gpc_exception functions below 10
Move multiple if statements from those functions to sub
functions to reduce complexity
Jira NVGPU-3975
Change-Id: I443a26d8addf2129bd5b3e512a59f4d4ecc922ea
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191296
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Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.
The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.
JIRA NVGPU-3820
Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
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Add support gr_prepare for sw and hw.
Add needed registers using nvgpu_posix_io_add_reg_space calls.
Add unit tests covering following functions
nvgpu_gr_prepare_sw
nvgpu_gr_enable_hw
install-unit.sh modified to copy the firmware binaries under
nvgpu-unit/firmware directory
Currently the gr_init_prepare test is called as part of the
gr_config test, later this will be moved as separate unit test.
Jira NVGPU-3582
Bug 2693908
Change-Id: If8f5ac4988deba0db477b2177981f7912bdb8eec
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191254
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Add posix support for nvgpu_request_firmware and
nvgpu_release_firmware calls.
In x86, needed firmware are copied under userspace/firmware
directory.For jetson, firmware files will be copied under
nvgpu_unit/firmware directory.
Update Makefile.tmk to copy firmware in systemimage under
nvgpu_unit/firmware directory.
Jira NVGPU-3582
Bug 2693908
Change-Id: I5f5e5819dc5501e587bc8afc0a3944c18a8e9bef
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189493
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Advisory Rule 5.9 states that identifiers that define objects or
functions with internal linkage should be unique.
This change eliminates an Advisory Rule 5.9 violation in our falcon
code involving falcon_sw_init() by renaming it to
falcon_sw_chip_init().
Jira NVGPU-3178
Change-Id: Ia064f383131ad3a7db56b5dcc02c754a7cc3e6f6
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2190094
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Advisory Rule 5.9 states that identifiers that define objects or functions
with internal linkage should be unique.
This change eliminates an Advisory Rule 5.9 violation in our the mmu and
fifo fault handling code involving the 'invalid_str' variable by
renaming it to 'mmufault_invalid_str' and 'ctxsw_status_invalid_str'
respectively.
Jira NVGPU-3178
Change-Id: I9b60c8441fc8e0423151f1bf116d21489af78bf0
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2190084
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The following misra violations are fixed in the current patch.
1) misra_c_2012_directive_4_7_violation: Calling function
"nvgpu_report_host_err" which returns error information without testing
the error information.
2) misra_c_2012_directive_4_7_violation: The variable "intr_0_en_mask"
which contains error information hasn't been tested.
3) misra_c_2012_directive_4_7_violation: Calling function
"gv11b_fifo_intr_0_error_mask(g)" which returns error information
without testing the error information.
4) misra_c_2012_rule_8_6_violation: "gk20a_fifo_bar1_snooping_disable"
is declared but never defined.
5) misra_c_2012_rule_8_6_violation: "gm20b_fuse_check_priv_security" is
declared but never defined.
6) misra_c_2012_rule_8_6_violation: "gm20b_fuse_status_opt_gpc" is
declared but never defined.
Jira NVGPU-3881
Change-Id: I731cd1d99649e07cb39aa75c4715e17eedd4d927
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2188161
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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